Design Engineer

Mostafa Mohiuddin Hasan

***** ***** **** ****, ***#1306, San Antonio, TX 78256

● *.*.*******@*****.*** ● 210-***-**** ● www.linkedin.com/in/mostafa-hasan SUMMARY

Skilled in digital system design with exposure to RTL Design (Verilog), functional verification, logic synthesis, static timing analysis, placement and routing, manual layout design

Proficient in digital design verification, DFT architectures and various DFT techniques, ATPG techniques, logic and fault simulation, power estimation and optimization

Comprehensive understanding of microprocessor design, microprocessor programming, computer architecture

Experienced in object oriented programming C++ (6 years) and scripting language Perl (2 years) TECHNICAL SKILLS

Logic Synthesis Tools: Xilinx Vivado, Xilinx ISE, Cadence RTL Compiler

Layout Tools: Cadence Virtuoso, Cadence Encounter

Simulation Tools: Modelsim, Altera Quartus, SPICE, SimpleScalar

Timing and Power Analysis Tool: Synopsys PrimeTime

Operating Systems: Linux/Unix, Windows

EDUCATION

Master of Science in Electrical Engineering GPA: 3.95 The University of Texas at San Antonio Graduated: August 2017 Bachelor of Science in Electrical & Electronics Engineering GPA: 3.75 Ahsanullah University of Science and Technology, Dhaka, Bangladesh Graduated: July 2015 RELEVANT PROJECTS

Light-weight Run-time Monitoring System for Examination of Internet-of-Things Devices

(Master's Thesis)

Designed hardware based function call and memory access monitoring modules using Verilog

Utilized Xilinx ISE design suite for RTL development and functional simulation

Integrated developed modules in a 32-bit ARM SoC and verified functionality with Xilinx ISIM

Synthesized the design at 180nm with RTL Compiler, followed by PnR in Cadence Encounter Design and simulation of a 32-bit MIPS Microprocessor

Developed Verilog code for a 32-bit MIPS microprocessor and simulated it in Xilinx Vivado

Used Cadence RTL Compiler to synthesize and Cadence Encounter to generate the layout

Conducted critical path analysis, static timing and power analysis using Synopsys Primetime Perceptron Based Branch Prediction.

Implemented the predictor on SimpleScalar Platform

Characterized prediction performance by running benchmark suites and compared prediction rate with conventional methods

A MIPS Disassembler.

Developed a MIPS binary disassembler using object oriented programming in C++

Verified functionality and correctness with multiple binary files and corresponding assembly code A Cache Performance Simulator.

Developed the simulator on C++

Programmed the simulator to read in a cache configuration file and a memory address trace file for generating the cache hit/miss behavior on each of the memory addresses, and finally output the cache performance results (miss rate)

A Mini Social Network.

Designed a secured and well-maintained mini social network software with complex object oriented programming on C++ environment

Participated in planning for this software development process, captured requirements, designed the architecture of the software, tested the software, deliver the outcome, and showed how to maintain it WORK EXPERIENCE

Graduate Research Assistant May 2016 – Present

Digital System Design Laboratory, Electrical & Computer Engineering Department, UTSA

Participated in research of a standardized light-weight examination method, contributing to a master's thesis with objective to analyze practicality and effectiveness of the method

Implemented and integrated monitoring module for the examination method with the ARM-compatible Amber processor

Graduate Teaching Assistant / Graduate Student Assistant September 2016 - August 2017 Electrical & Computer Engineering Department, UTSA

Conduct tutoring sessions and complete assigned grading for 170+ students in timely manner in the Electronic Devices, Electric Circuits and Network Theory courses Facilities Student Staff May 2016 - August 2016

UTSA Housing & Residence life, UTSA

Assisted the full-time housing and residence life facilities staff in performing routine maintenance and custodial work

Management Trainee Intern March 2015 - May 2015

Radio Network Planning Department, Robi Axiata Limited, Dhaka, Bangladesh

Collaborated with 10+ full time staff from design team in engaged network planning, frequency planning, updating parameters of new cellular networks RELEVANT COURSES

VLSI System Design

Computer Architecture

Solid State Devices

Engineering Programming

VLSI Testing

Superscalar Processor Design

Microprocessor Interface & System Design

Processing & Fabrication Technology

ACADEMIC HONORS

UTSA ECE Department Pioneer Scholarship, Recipient August 2016- August 2017

UTSA International Grant, Recipient August 2016- August 2017

Dean’s List, AUST July 2015

Department Merit List, AUST April 2011- April 2014

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