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Electrical Engineer Design

Location:
Austin, Texas, United States
Posted:
May 31, 2018

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Resume:

Gary Kurtzman (ac5o1p@r.postjobfree.com) 512-***-****)

Electrical Engineer with 40 years in Analog/RF/PLL IC engineering (design, debug, test).

Extensive analog circuit design and debug via test bench analysis, micro probing and FIB.

Test program generation and debug.

Expert with Cadence ADE toolset.

Experience with factory and test personnel on IC problems.

Extensive experience with LVS & DRC tools (Calibre & Cadence)

Experienced with Cadence circuit layout and layout XL.

Test chip creation (floor planning, DRC & LVS).

Work History:

Analog IC Design Contractor @ IBM/Global Foundries (1/1/2015 to Present)

Member of the Technical Staff, Ambiq Micro (10/2013 to 6/2014)

Senior Member of the Technical Staff, Motorola/Freescale (07/1978 to 04/2013)

Education:

The University of Texas at Arlington

MS, Electrical and Electronics Engineering, 1980 - 1982

University of Wisconsin-Madison

BS, ECE, 1974 - 1978

Analog IC Designer with extensive design experience in:

Analog Bipolar design including: Opamps, buffers, level shifters. ECL/CML/I2L logic.

CMOS PLL block design including: Dual Modulus Prescaler, Sample & Hold Phase Detector, Lock Detector, Adaptive Loop Filter.

BICMOS Zero IF Receiver block design including: Low Noise LDO Regulator, Bandgap, RF Buffer, RF Gilbert Mixer, RF AGC, Gm-C based filtering, RC based filtering, PLL demodulator, FM discriminator, RSSI, PLL AFC, DC Offset correction, Phase Shifting, Dual Port Modulation & Demodulation, Log Amplifier, RF Peak detector, voltage multiplier.

PLL & PLL block design including: LC VCO (< 5Ghz), Ring Oscillator VCO ( < 600 MHz), Charge Pump Phase Detector, XOR Phase Detector, On Chip Loop Filtering. PLL parameter calibration (VCO KV and center frequency, Loop Filter bandwidth), Lock Detectors, High speed

( < 5 Ghz) dividers.

Design of Low TIE Jitter PLL for 4GDigRF interface. Design of low jitter PLL’s for ADC’s.

Design of PLL for FM AMPS, NAMPS, GSM (2G, 3G, 4G), DVBT/H, Bluetooth, Pico-cell, BTLE.

Design of Sub Threshold Oscillators and Voltage/Current references.

Design PLL blocks for 30G & 56G SERDES PLL's in 14nm & 7nm FINFET(Regulators, Bandgaps, Opamps, VCO's (3 Ghz to 16Ghz) Buffers, Dividers, Filters)

Top level SERDES PLL design (Rj, Dj, PLL Coupling, BW, Lock Time)

Design and analysis of inductor structures with EMX and VeloceRF.

Accomplishments: 8 Issued Patents



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