| Resume alert | Resumes 41 - 50 of 111 |
Information Technology Customer Service
Austin, TX, 78717
... Technology Organization Right sized Global technology organization eliminating approximately 35 positions while improving release cadence and code quality Drove PaaS standards to ensure all software releases are backwards compatible and third party ... - 2017 Jan 09
... Technology Organization Right sized Global technology organization eliminating approximately 35 positions while improving release cadence and code quality Drove PaaS standards to ensure all software releases are backwards compatible and third party ... - 2017 Jan 09
Computer Engineering Software Engineer
Austin, TX
... June 2013 Bachelor of Technology – Electronics: VES Institute of Technology [GPA: 3.86/4] SKILLS: Programming Languages: Java, JSF, JSON, C/C++, Verilog, VHDL, Python Application Software: Cadence, MATLAB, Xilinx ISE, ModelSIM, AUTOCAD, EAGLE, ... - 2016 Nov 23
... June 2013 Bachelor of Technology – Electronics: VES Institute of Technology [GPA: 3.86/4] SKILLS: Programming Languages: Java, JSF, JSON, C/C++, Verilog, VHDL, Python Application Software: Cadence, MATLAB, Xilinx ISE, ModelSIM, AUTOCAD, EAGLE, ... - 2016 Nov 23
Design Engineer Electrical Engineering
Austin, TX
... • Design Software: SILVACO, SCHRED, Cadence, Mentor Graphics, MAGIC, SimpleScalar, VHDL, HSpice, IRSim, OrCAD, Pspice, Matlab, MathCAD, Tecplot. • Languages: C, System verilog, Perl, TCL/TK, LATEX. EDUCATION Graduate in Electrical Engineering (2005 ... - 2016 Sep 04
... • Design Software: SILVACO, SCHRED, Cadence, Mentor Graphics, MAGIC, SimpleScalar, VHDL, HSpice, IRSim, OrCAD, Pspice, Matlab, MathCAD, Tecplot. • Languages: C, System verilog, Perl, TCL/TK, LATEX. EDUCATION Graduate in Electrical Engineering (2005 ... - 2016 Sep 04
RTL to GDS II, Verilog, System Verilog, TCL, Perl, C
Austin, TX
... Project “Block level design of LEON in 45nm” Technical Lab Assistant, University of Missouri Kansas City Oct’14 – May’16 Role Assisting students with Technical tools and Software usage (Cadence, MS-Office) Solving technical problems both hardware ... - 2016 Aug 29
... Project “Block level design of LEON in 45nm” Technical Lab Assistant, University of Missouri Kansas City Oct’14 – May’16 Role Assisting students with Technical tools and Software usage (Cadence, MS-Office) Solving technical problems both hardware ... - 2016 Aug 29
Engineering Service
Austin, TX, 78741
... Angular JS, SQL, Guava Technology Skill: Google App Engine, Linux, Git, perforce, Android, Database, Testing, gdb Internship Cadence Design System (Software Internship) Feb.2016– May.2016 Cleaning up libraries with boost, include using boost file ... - 2016 Jul 26
... Angular JS, SQL, Guava Technology Skill: Google App Engine, Linux, Git, perforce, Android, Database, Testing, gdb Internship Cadence Design System (Software Internship) Feb.2016– May.2016 Cleaning up libraries with boost, include using boost file ... - 2016 Jul 26
Software Engr., Product Development/Management, Business Development
Austin, TX
... Instruments ● Created unique technology that was leveraged as a distinct offering of electromigration solutions for NEC Cadence Design Systems, N oida, UP, India 1999 - 2007 Member of Consulting Staff (2006 - 2007) ● Invented new cell selection ... - 2016 Apr 11
... Instruments ● Created unique technology that was leveraged as a distinct offering of electromigration solutions for NEC Cadence Design Systems, N oida, UP, India 1999 - 2007 Member of Consulting Staff (2006 - 2007) ● Invented new cell selection ... - 2016 Apr 11
Design Assistant
Austin, TX
... chamber, oscilloscope, and soldering station In-depth understanding of RF systems, IC design tools and simulators: Cadence (SpectreRF, APS, Virtuoso) and useful softwares: MATLAB, EXCEL Knowledge of LTE UE standard: interpretation of system ... - 2015 Jul 06
... chamber, oscilloscope, and soldering station In-depth understanding of RF systems, IC design tools and simulators: Cadence (SpectreRF, APS, Virtuoso) and useful softwares: MATLAB, EXCEL Knowledge of LTE UE standard: interpretation of system ... - 2015 Jul 06
Engineer Process
Austin, TX
... Experience in the design of Wire Bond Out, C4 Bump, Wafer Level Burn-in, Copper Metal Technology using OPC, and Tiling mask procedures and techniques Experience with Cadence, K2, Mentor Graphics Calibre and Cats, CAD Layout, Unix, Cats, Perl, ... - 2015 Apr 13
... Experience in the design of Wire Bond Out, C4 Bump, Wafer Level Burn-in, Copper Metal Technology using OPC, and Tiling mask procedures and techniques Experience with Cadence, K2, Mentor Graphics Calibre and Cats, CAD Layout, Unix, Cats, Perl, ... - 2015 Apr 13
Electronics Engineer Technician
Austin, TX
... Microsoft Visual Programming • Microsoft Windows (all versions) • Linux (most versions) • Mentor Graphics • Microsoft Office • Cadence • Proprietary Equipment Tools for AMD, Neteffect, Intel, and US Navy PROFESSIONAL EXPERIENCE 2008 – Present INTEL ... - 2015 Apr 01
... Microsoft Visual Programming • Microsoft Windows (all versions) • Linux (most versions) • Mentor Graphics • Microsoft Office • Cadence • Proprietary Equipment Tools for AMD, Neteffect, Intel, and US Navy PROFESSIONAL EXPERIENCE 2008 – Present INTEL ... - 2015 Apr 01
ESL Instructor, Technical Writer, Editor
Georgetown, TX
... Cadence Design Systems, Inc. Education Services Over 25 years in editing and writing in this high-tech firm, contributing in the following areas: Course Editing Technical Writing Training and Mentoring Template Development Course Editing Edited over ... - 2015 Mar 26
... Cadence Design Systems, Inc. Education Services Over 25 years in editing and writing in this high-tech firm, contributing in the following areas: Course Editing Technical Writing Training and Mentoring Template Development Course Editing Edited over ... - 2015 Mar 26