Engineer Engineering

Shao-Heng Chou

Address: **** ********** ** ****** ****-B, AUSTIN, Texas 78741 USA

Phone:1-512-***-****

E-mail: *********@*****.***

Profile ● Circuit Design Courses of VLSI, VLSI Physical Design Automation, VLSI Verification, UVM, Analog IC

● Strong Device Analysis skills with CMOS/FinFET characterization and TCAD Device simulation Education University of Texas at Austin, Austin, Texas, USA 2017-2019 MS : Electrical and Computer Engineering, GPA : 3.8/4.0 National Chiao-Tung University, Hsinchu, Taiwan 2010 - 2012 MS : Electronics Engineering, GPA : 3.8/4.0

National Chiao-Tung University, Hsinchu, Taiwan 2006 - 2010 BS : Electronics Engineering, GPA : 3.6/4.0

Work

Experience

TSMC ( Taiwan Semiconductor Manufacturing Co., Ltd.), Hsinchu, Taiwan 2012 – 2015 SPICE MODEL RD Engineer

● Combine MOL flow with FEOL BSIM model for 28nm and latest technology nodes.

● Redesign the BEOL model of Self Aligned Double Pattern (Under Pitch 44nm) using Monte Carlo simulation for corner prediction and provide the color metal model.

● To tighten MOL and BEOL corners, develop CB_T, CW_T, RCB_T and RCW_T corners with 2.4 and 1.5 sigmas.

● Work on Model wrapper such as TMI for simulation efficiency (aging model in BSIM).

● Be a Python TA in TSMC Model Division for teaching Python script. Device RD Engineer (14nm ~ 5nm)

● FinFET SOI device development and analysis for IO device in 14nm.

● Define testline for contact resistance and MOL for 5nm devices. Academia Sinica, Taipei, Taiwan 2015 – 2016

Research Assistant

● 2D material growth using low temperature ALD process. Cirrus Logic, TX Austin, U.S.A. 2018/05 – 2018/08

Device Physics Intern

● Investigation of N55 Poly Resistor TCR in corners.

● Comparison of CMOS 1/f noise between foundries.

Cirrus Logic, TX Austin, U.S.A. 2019/05 – 2019/08

Library Characterization Intern

● Comparison of characterization tool between Synposys and Cadence. Skills ● Programming: C/C++, Perl, Python, SystemVerilog

● BEOL RC Deck Modeling and CMOS/FinFET Device Characterization Publication 1. S.-H. Chou, M.-L. Fan, and Pin Su, "Investigation and Comparison of Work Function Variation for FinFET and UTB SOI Devices Using Voronoi Approach," IEEE Transactions on Devices, vol. 60, no. 4, pp. 1485-1489, April 2013. 2. S.-H. Chao, M.-L. Fan, and Pin Su, "Investigation and Comparison of Work Function Variation for FinFET and Ultra-Thin-Body SOI Devices Using a Voronoi Approach," Extended Abstracts of the 2012 International Conference on Solid State Devices and Materials (SSDM), Kyoto, Japan, September 2012.

3. C.-W. Yang, S.-H. Chao, and Pin Su, "Simulation of Grain-Boundary Induced Vth Variability in Stackable NAND Flash Using a Voronoi Approach," 12th Non-Volatile Memory Technology Symposium (NVMTS 2012), Singapore, November 2012. Patent 1. Mixing Knowledge Sources for RC Extraction (co-inventor)- US Patent #9218448 - Resistive capacitance determination method for multiple-patterning-multiple spacer integrated circuit layout

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