Design Engineer Software Developer

DILESH MUTTA

*****.******@*****.***, https://www.linkedin.com/in/dilesh-mutta, +1-253-***-****, Austin, TX 78729

Physical Design Engineer Hardware Design Engineer

SUMMARY:

Passionate Electrical IC Design Engineer, with a focus on Digital Circuits Design and an interest in applying the knowledge to computer architecture and neuromorphic chips. Highly skilled in ASIC/VLSI design and proficient in physical design flow and layout extractions, timing analysis, clocking of the circuits, DRC check, LVS check using design tool like Cadence, Mentor Graphics Calibre etc.

EDUCATION:

University at Buffalo, US, Master of Science in Electrical Engineering (GPA: -3.65/4) Sep 2018

JNTUH, India, Bachelor of Technology in Electrical Engineering (GPA: -3.8/4) May 2015

PROFESSIONAL EXPERIENCE:

Research Assistant Mixed Signal Design group AUG 2017 - Present

Designed schematic and layout of a 512-bit SRAM with two 256-bit banks, address decoder, Pre-charge, Read/Write circuitry and Sense amplifiers.

Modeled a python script for simulation and result verification of SRAM.

Software Developer GGk Technologies Private Limited JAN 2015 – JULY 2016

Worked as an application developer and worked on MySQL database in a team of 6 people as a back-end engineer.

Developed a web-based chat application in .NET Framework and C++. Helped connect customer with customer care.

Prepared detailed reports based on the results of reviews of documentation and specification.

PCB Design Engineer JNTUH Technical Innovation Team JAN 2014 – JAN 2015

Performed PCB designs using Altium and soldering of designs implemented on LTspice and multisim.

Analyzed the designs of Amplifiers, Active Filters and Oscillators soldered on PCB and tested using lab equipment.

TECHNICAL SKILLS:

Programming/Scripting languages: System Verilog, Verilog, VHDL, Python, Perl, C, C++, Shell scripting in Linux, TCL

CAD Tools: ModelSim, Xilinx, Quartus II, MATLAB, LabVIEW, Cadence (Virtuoso XL, Innovus, Spectre and Layout), Altium, QuestaSim, Synopsys

Physical Design Flow: Floor planning, Placement and routing, Static Timing analysis, Clock Tree synthesis, Timing Closure, netlist extraction, power integrity and area optimization, DRC, LVS, netlist extraction

Lab Equipment: Oscilloscope, Function Generators, VNA, Spectrum Analyzer, Logic Analyzer, Multimeter

ACADEMICS PROJECTS:

DESIGN OF SOUKUP’S MAZE ROUTING ALGORITHM [Tool: NC SIM, DC Compiler]

Designed an innovative FSM based 8x8 maze router using the Soukup’s algorithm to find path between two targets.

Block Level placement and routing was performed this helped me reduce cross-talk noise.

Synthesized the design using Synopsys design compiler.

STATIC TIMING ANALYSIS (STA) OF A SYNTHESIZABLE DIGITAL CIRCUIT [Tools: PrimeTime and PERL]

Designed constraints, generated setup – hold time and area reports. Analyzed the results and derived data arrival time, data setup required time, data hold required time, setup slack and hold slack.

Performed static timing analysis using PrimeTime and PERL commands ( Scripting language).

Developed an efficient PERL algorithm to analyze repeater flop to flop distances.

DESIGN OF AXI - OCP CONVERTER [Tool: ModelSim]

Constructed interfaces for Master, Slave, Arbiter, Interconnect and other complex blocks.

Made use of state machines to prioritize the function.

Used an online tool to simulate and logic debugging of the conversion.

VERIFICATION OF ASYNCHRONOUS FIFO – SystemVerilog [Tool: QuestaSim]

• Verified a class-based test-bench with interface, driver, monitor and scoreboard.

• Generated random test data for functional testing and assertions were used.

IC DESIGN OF A PHASED LOCKED LOOP (PLL) [Tool: Cadence Spectre, Calibre]

Analyzed and studied the design of a digital phase locked loop and then implemented the design in cadence.

Constructed PFD, charge pump. loop filter and current starved VCO in TSMC 65nm technology.

OTHER PROJECTS:

FPGA Prototyping of Bi-Directional Counter synthesized on Altera Cyclone IV FPGA board.

Design of a simple 5 stage pipeline using rtl coding – verilog

Designed a Colpitts’s Voltage Controlled Oscillator in ADS, performed analysis using spectrum analyzer.

FPGA implementation of Collision Detection For 3d Printers in Xilinx ISE.

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