NASRIN SULTANA

***** ******* *****, ******, ** **717. E-mail: ac6atx@r.postjobfree.com

Phone: 512-***-**** ac6atx@r.postjobfree.com

OBJECTIVE:

Electrical Engineer who has expertise in designing high performance microprocessor (ASIC design) in latest 7nm technology, including schematic, layout, simulation, timing analysis

(STA)/closure, physical design checks, logical to physical verification using semi-custom and large block synthesis techniques.

PROFESSIONAL EXPERIENCE:

IBM (April 2014- present), in Instruction Sequencing Unit (ISU) as Hardware Engineer: Responsibilities

• Work as circuit/Physical designer/owner for different high performance macros or blocks or ASIC design in 14nm and 7nm in 3.5 GHz frequency or more.

• Responsible for all phases of projects including design, floor planning, pin placement, schematic development, layout, verification of a next generation block/macro or ASIC block.

• Run the synthesis tools to implement the block from RTL to layout in form of OASIS

(newer format of GDSII) using Cadence Space-based Router (equivalent to Synopsys ICC).

• Analyze the timing of the circuit of a block or macro and redesign if necessary.

• Perform block level floor planning, placement and routing.

• Hand on implementation of schematic of part of block design in Cadence to meet timing, power, space requirement, which, tools can’t handle due to high congestion.

• Design flat or hierarchical to use the sub-cells several times as needed for efficient design.

• Create structured vhdl, cell placement file out of the schematic for optimum design using LAP (layout Automation).

• Physically Pre-place the cells like latches, LCB (local clock buffer), logic gates etc in the layout to get the desired design, least wire delays, optimized critical path -- ultimate timing and design closure.

• Change the assertions of the pins, change their position (supporting the blockages) or metal layer to get desired timing results without any errors using IPP (initial pin placement).

• Analyzed clock domain, work with logic designer to change vhdl to stop unnecessary clocking and save power and leakage.

• Generate static timing analysis(STA). Support and maintain SOC level timing constraints.

• Close timing and maintain timing closure in core/chip level. Fix any timing fail.

• Use Einstimer (similar to Primetime) and VLTR to analyze timing and close.

• Implement ECO’s to fix functional bugs, timing fails etc. used both manual ECO or tool based ECO.

• Compromise the metal layer distribution with integrator. Change the metal layer for timing requirement. Also work closely with integrator to support SOC timing closure in different ways like buffer distribution for a net, moving a pin in block etc.

• Layout, autoAnalysis, abstract/cover etc generation.

• Layout Analysis, Gate level Sign off Extraction and Analysis Clock Pin Annotation (CPA), early and late mode timing, scan DFT check, checking subsystem like Abstract, autoAnalysis, noise impact on Function(NRA), Parasitic Extraction etc.

• Run physical verification flow like Power Analysis(EPA) and Electrical Rules checking(EIN/ECA/PWD), signal/ power electromigration (EM), IR etc. If any checking fails, change the design to fix it.

• Checking subsystems like abstract (AMC), autoAnalysis (CSS) etc.

• Test Analysis Testbench analysis and test model generation (GTM), autoRouted vs test model equivalency check (VER), autoRouted vs VHDL equivalency check (LGA)

• Change the layout of the design to clean LVS, DRC, Methodology rule check (NMC), Design rule Pattern Matching Checking (DPM), GL1Compare for ECO etc. using Cadence Physical Verification System (PVS).

• Customize the macro layout to ensure the correctness design and rout ability.

• Power and noise analysis, Low power and low noise design. Use efinale to change the gate size to save power without compromising the design, i.e., timing. Changed the threshold voltages to be low to get better timing at the cost of leakage or vice versa.

• sub-module level integration to save area, logic, timing etc. examined the advantages whether merging blocks/macros improving unit timing, saving area, removes logic etc.

• Designing standard library cells and using those cells in synthesis flow.

• Work on power management. Calculate power of latches and LCBs to find different power optimized scenarios like functional clock gating, different clock domain etc.

• work with logic owners to move logic from one block to another to make them work efficiently.

• Spice simulation to see the timing possibilities using PowerSpice or EinsTLT before synthesis.

• Verify correctness of the schematic using verity in Cadence.

• Developed dedicated environments and tools using LINUX, while driving a complex process of exercising the design to verify it’s logical and design correctness. INTEL (May 2012-March 2014), in Mixed Signal Validation Group as Graduate Intern Technical:

Responsibilities

• Developed dedicated verification environments and tools using UNIX, while driving a complex process of exercising the design to verify its logical correctness.

• Used full featured standalone next generation transistor level simulation engine XA that delivers SPICE accuracy while maintaining Fast-SPICE performance and capacity.

• Analyzed the analog functionality to ensure that both RTL and circuit designers correctly implemented the circuit specification and that the circuit complies with all required external and platform specifications,

• Implemented design improvement, tool and methodology refinement in RTL model and SPICE NETLIST,

• Validated design by identifying and exercising special cases for specific test,

• Debugged performance issues and test failures,

• Provided robust functional fixes,

• Authorized and implemented test plans to provide test coverage for new architecture features,

• Strong discipline and attention to detail in ensuring effective and high quality validation that minimizes bug escapes,

• Reviewed the validation with relevant groups,

• Gained domain expertise to be able to validate effectively independently,

• Ensured the quality of multi-user, multi-site validation source code,

• Worked in a cross-site cross-team environment, i.e., with design engineers, digital validators, other team members.

RRE Austin solar (May 2011-Aug 2011) as Engineering Intern: Responsibilities

Research and review of RFP request response, project management, Webpage development supervision, Efficient Multi-User document control system (SharePoint), Providing and maintaining support for File Transfer Protocol (FTP) etc. TECHNICAL AND COMPUTER SKILLS:

Circuit and Device Simulation Software: Cadence, HSPICE, PSPICE, DHCH, GUIDE.

Routing tools: RLMBuild, eFinale, finale, DeltaSyn, ECO.

Graphical and timing analyzer tool: EinsTLT, VLTR.

Operating System: Windows, UNIX, LINUX.

Office tools: Microsoft word, Excel, powerpoint.

Languages: VHDL(behavioral and structured), C, assembly language for PIC series microcontrollers, scripts in Unix/Linux.

EDUCATION:

M.Sc. in Electrical and Computer Engineering

University of Texas, Austin. GPA: 3.52/4.00.

B.Sc. in Electrical and Electronic Engineering

Bangladesh University of Engineering and Technology, Dhaka, Bangladesh. GPA: 3.87/4.00.

HONORS:

Received “First Patent Application Invention Achievement Award” from IBM.

Recommended by manager in LinkedIn.

https://www.linkedin.com/in/nasrin-sultana-2715594

Published 1 journal and 3 conference papers.

University Merit Scholarship.

Dean’s List Award.

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