| Resume alert | Resumes 101 - 110 of 448 |
Electrical Engineering,Analog & Digital Design,Hardware Design enginee
Mountain View, CA
... 3 4 Worked on ASIC based design using Verilog. 3 4 Hands on experience of HW design tools ( LTspice, OrCAD, Ultium Designer) 3 4 Good debugging skills. 3 4 Ability to learn new technologies, team player, goal-oriented and highly motivated. 3 4 ... - 2018 Feb 14
... 3 4 Worked on ASIC based design using Verilog. 3 4 Hands on experience of HW design tools ( LTspice, OrCAD, Ultium Designer) 3 4 Good debugging skills. 3 4 Ability to learn new technologies, team player, goal-oriented and highly motivated. 3 4 ... - 2018 Feb 14
Analog IC Design Engineer
Fremont, CA
... Independent Research: Co-simulation between CADENCE and MATLAB/Simulink using Verilog-AMS simulator Worked on Co-simulation between CADENCE and MATLAB/Simulink using Verilog-AMS simulator in CADENCE and verified the work with a simple CMOS Inverter ... - 2018 Feb 08
... Independent Research: Co-simulation between CADENCE and MATLAB/Simulink using Verilog-AMS simulator Worked on Co-simulation between CADENCE and MATLAB/Simulink using Verilog-AMS simulator in CADENCE and verified the work with a simple CMOS Inverter ... - 2018 Feb 08
Electrical Engineer Engineering
San Jose, CA
... Hardware Descriptive Languages: Verilog HDL, System Verilog. Others: RTL Design using Verilog, Debug, Power Supply, Logic Analyzer, Oscilloscope, DMM, soldering rework of SMT. PROJECTS • Implementation of Advanced High-performance Bus based DDR ... - 2018 Feb 06
... Hardware Descriptive Languages: Verilog HDL, System Verilog. Others: RTL Design using Verilog, Debug, Power Supply, Logic Analyzer, Oscilloscope, DMM, soldering rework of SMT. PROJECTS • Implementation of Advanced High-performance Bus based DDR ... - 2018 Feb 06
Engineer Professional Experience
San Jose, CA
... EDA tools Cadence Virtuoso (Schematic and Layout) • Proficient in analog circuit simulators Spectre and SPICE • Experience in Verilog and Python scripting • Familiar with Linux/Unix environments • Comprehensive knowledge of transistor level analog ... - 2018 Jan 23
... EDA tools Cadence Virtuoso (Schematic and Layout) • Proficient in analog circuit simulators Spectre and SPICE • Experience in Verilog and Python scripting • Familiar with Linux/Unix environments • Comprehensive knowledge of transistor level analog ... - 2018 Jan 23
Verilog, Perl, Digital IC design, FPGA/ASIC design, Physical Design
San Jose, CA
... 2011 GPA: 3.72/4.0, Electronic, Computer and Communication(ECC) SKILLS • Solid background on frontend and backend digital circuit design, 6-T cell SRAM design and FPGA design • Programming Language: C, Perl, TCL, Verilog • Software Package: Xilinx ... - 2018 Jan 11
... 2011 GPA: 3.72/4.0, Electronic, Computer and Communication(ECC) SKILLS • Solid background on frontend and backend digital circuit design, 6-T cell SRAM design and FPGA design • Programming Language: C, Perl, TCL, Verilog • Software Package: Xilinx ... - 2018 Jan 11
Verilog, System Verilog, SV Assertions, Physical Design, DFT
Campbell, CA
... SKILLS • Programming Languages : Proficiency Level Verilog, C : System Verilog, System Verilog Assertions: VHDL, PERL : Linux Shell Scripting, X86 Assembly : • Verification Methodologies: UVM • Design Tools: Cadence Virtuoso, Cadence NC Launch, ... - 2018 Jan 07
... SKILLS • Programming Languages : Proficiency Level Verilog, C : System Verilog, System Verilog Assertions: VHDL, PERL : Linux Shell Scripting, X86 Assembly : • Verification Methodologies: UVM • Design Tools: Cadence Virtuoso, Cadence NC Launch, ... - 2018 Jan 07
SQL Data Analyst
San Jose, CA
... 4) Verification of 10GB Ethernet MAC Core using System Verilog It was a hands-on opportunity to build a System Verilog class-based verification environment, otherwise known as the OOP Testbench, on a 10Gb Ethernet MAC Core design. The packet module ... - 2017 Dec 31
... 4) Verification of 10GB Ethernet MAC Core using System Verilog It was a hands-on opportunity to build a System Verilog class-based verification environment, otherwise known as the OOP Testbench, on a 10Gb Ethernet MAC Core design. The packet module ... - 2017 Dec 31
Design Engineer Professional Experience
San Jose, CA
... HDL language: VHDL and Verilog. Design Implementation Activities: Create block level timing constraints and IP constraints integration. Logic synthesis & Clock gating insertion using DC/DCT. Floorplaning using ICC/Innovus. Powergrid generation ... - 2017 Dec 21
... HDL language: VHDL and Verilog. Design Implementation Activities: Create block level timing constraints and IP constraints integration. Logic synthesis & Clock gating insertion using DC/DCT. Floorplaning using ICC/Innovus. Powergrid generation ... - 2017 Dec 21
Engineer Design
Fremont, CA
... Logic design, Analog circuit design, High bit rate digital (HDSL/HDSL2/SHDSL AND ADSL) line card design Designed CPLD for glue logic design using Verilog& VHDL . Schematic capture using ORCAD, VIEW-DRAW and CONCEPT HDL. During design phase, closely ... - 2017 Dec 13
... Logic design, Analog circuit design, High bit rate digital (HDSL/HDSL2/SHDSL AND ADSL) line card design Designed CPLD for glue logic design using Verilog& VHDL . Schematic capture using ORCAD, VIEW-DRAW and CONCEPT HDL. During design phase, closely ... - 2017 Dec 13
ASIC Verification Engineer, NVIDIA
San Jose, CA, 95134
... interface with DPI-C o Profiled the entire register-access and memory-access infrastructure at full-chip level using C++/System- Verilog to gauge scope for future optimizations and reduced runtime from days to hours o Detailed understanding of GPU ... - 2017 Dec 12
... interface with DPI-C o Profiled the entire register-access and memory-access infrastructure at full-chip level using C++/System- Verilog to gauge scope for future optimizations and reduced runtime from days to hours o Detailed understanding of GPU ... - 2017 Dec 12