Design Engineer Professional Experience

Jason Hu (US Citizen)

408-***-**** ac3rzd@r.postjobfree.com

QUALIFICATIONS SUMMARY

A senior Physical Design Engineer with 18+ years of hands-on experience in all aspects of physical design and verification process using industry standard EDA tools.

Expertise includes Place & Route design automation utilizing ICC & TCL scripts for ASIC physical implementation, automated design library/collateral view generation using ICC and Cadence Virtuoso, block-level and chip-level layout verification using ICV, Calibre and Redhawk, static timing analysis (STA) and timing closure, signal integrity, low power implementation,

(LVS/DRC/ERC/ANT and LEC fixes).

Extensive experience of floor-planning utilizing ICC & Innovus, Timing and congestion analysis using Design Compiler and IC Compiler (ICC), DFM using IC Compiler, CTS, timing to meet design requirements for area, power & timing.

Extensive experience in physical library development and EDA tools support

Experienced in block timing-driven synthesis, P&R, CTS, STA and timing closure.

Implemented, Integrated, and Verified several designs both at unit, block and top level.

Proficient in all stages of the chip design cycle and experienced in tape out with industry leading foundries, such as Intel Custom Foundry and TSMC.

Outstanding interpersonal skills in teams as well as an independent individual contributor. TECHNICAL SKILLS

EDA tools:

Design Compiler (DC-topo), StarRC, PrimeTime, Cadence SOC Encounter, IC Compiler (ICC), Mentor Calibre, Cadence Virtuoso.

Scripting Languages: Tcl, Cshell, Makefile.

HDL language: VHDL and Verilog.

Design Implementation Activities:

Create block level timing constraints and IP constraints integration.

Logic synthesis & Clock gating insertion using DC/DCT.

Floorplaning using ICC/Innovus.

Powergrid generation script using Astro.

Clock Tree Synthesis (CTS) and Place and Route (P&R) using ICC.

Timing closure, ECO process using PrimeTime DMSA and ICC. Other Applications:

CVS, ClearCase, DesignSync, VNC, NoMachine, Exceed on Demand (EOD), Word, Excel, PowerPoint. Other EDA tools:

Avanti Suite (Planet, Saturn, Apollo), Cadence Suite (Virtuoso, SE), AutoCAD, Matlab. PROFESSIONAL EXPERIENCE

Marvell Semiconductors, Inc., San Jose, CA 1999 - 2016 Senior Physical Design Engineer

Accomplishments

I've done mostly the networking switch chips as well as SOC chips.

For full chip design, I was involving very early at development stage to provide several floorplans for the chip architect to review and select. I'm also partitioned some of the big chips and provided IPs so more chips can use the same IPs.

Completed several chips from floorplanning/ Place-n-route to tapeout (including LVS/DRC/ERC/ANT, Timing Closure, debugging / fixes), block-level / chip-level, Power analysis using Astro/ICC

Layout physical verification and cleanup using ICV & Calibre.

Multi-tasking on multiple tapeouts for different projects (350nm / 250nm / 180nm / 90nm / 65nm / 35nm / 28nm / 14nm) simultaneously.

In parallel trained many juniors on Place-n-route and layout designs

Completed fully custom design stdcell layout library set Intel Corp. (formerly Level One Communications), San Jose, CA 1996 - 1999 Senior Physical Mask Design Engineer

Custom Layout Design, from floorplanning to tapeout, including stdcell layout, using Cadence layout tool Auto P&R, from floorplanning to tapeout (including LVS/DRC fixes), block-level / chip-level, using Astro. Accomplishments

Completed Fully custom design stdcell cell layout library set, using Cadence Virtuoso.

Completed several chips doing Place-n-route from floorplanning to tape-out (including LVS/DRC debugging / fixes), block-level / chip-level using Astro.

In parallel to above main projects, completed multiple tape-outs (derivatives) for multiple projects (different technologies) simultaneously.

Multi-tasking on multiple tape-outs for different projects (350nm / 250nm) simultaneously.

In parallel trained many juniors on Place-n-route and layout designs EDUCATION

AA Degree in EE, Sacramento City College, Sacramento, CA

Contact this candidate