Engineer Design
Resume:
DEBASIS BHATTACHARJEE
FREMONT, CA 94539
Phone: 510-***-****
*******.****@*********.***
Objective:
Seeking a Sr. Hardware system design architect and/or board design position
Summary of Experience:
Telecommunication/networking hardware, board design engineer, delivered state of the art routers, access network and switching products.
Designed high density 40G Ethernet line card for data center application
Designed the first 100GE line card on router which was deployed at tier one service provider for Juniper Networks.
Designed high speed switch fabric board for multi-chassis core router application.
Architected and designed plug-and-play high-density 10Gig/1Gig line cards.
Designed high speed security processor board with XLR and Cavium security processor.
Designed high density GEPON 10Gigabit/12Gigabit line card for fiber to home application.
Designed switch-fabric for high speed Layer 2 /Layer3 IP access platform.
Designed POTS card for TDM, VOIP and VoATM application.
Designed and developed primary rate multiplexer (T1/E1), higher order multiplexer design (E3/E4 and DS3) and synchronous SDH).
Logic design, Analog circuit design, High bit rate digital (HDSL/HDSL2/SHDSL AND ADSL) line card design
Designed CPLD for glue logic design using Verilog& VHDL .
Schematic capture using ORCAD, VIEW-DRAW and CONCEPT HDL.
During design phase, closely work with cross functional team i.e. Power, SI, PCB layout, Mechanical, EMI and other groups.
Professional Experience
Cloudshiled/Lookingglass Cyber solution,
SanJose.
SR hardware Engineer.
Nov 2015 till date
System Desisgn & developed CPU balede, based upon dual CPU ( Thunder-x, 64 Arm core ) architecture for cyber security application This balde is being used for secured and nonsecured enviornment
Sytem Desisgn & developed Deep packet inspection module ( DPPM Blade ) with Regular Expression Engine ( REG-EX) functionality in cybersecurity domain for secure and non secure environment. I was responsibe for starting from system design, schematics generation, component placement, power analysis, Signal integrity rules writeup, working with PCB layout engineer,working with cross functional team,board btringup and debug and for pilot release of those two blades.
Cavium Inc, San Jose
Staff Hardware Engineer
Jan 2015 to Nov 2105
Bring-up and debug of 2S CRB based on ThunderX 48 ARM cores per device.
Review of schematic and layout of customer’s 1S and 2S designs.
Brocade Communication, San Jose
Staff Hardware Engineer
Oct 2012 to Jan 2015
Successfully designed, developed and validated 27x40GE LC (line card) for data center product (consisting of Gen1/2 and DDR3/2133Mbit/s interfaces).
Cooperated in development of 6x100GE and 48X10BT line card for datacenter procuct line (consisting of Gen1/2 and DDR3/2133Mbit/s interfaces).
Based on the functional specification, designed, developed, debugged and tested the CPLD Verilog code for successful shipping version of all above blades.
Lead Engineer and system architect for a 32Gbps backplane for Fiberchannel product line.
Juniper Networks Inc., Sunnyvale, CA
Staff Hardware Engineer
Jan 2007 to Oct 2012
Successfully designed and developed 100GE Ethernet card for T- and PTX-series router.
Lead the bringup of the linecard and chassis. Intercaces of the blade included: DDR3/1600Mbit/s,
PCIe Gen1/2, SERDES 10Gb/s and 40G/s CFP, electrical 100Gb/s links to CFP4 optics.
Designed and developed from concept through the development of a Switch Fabric board for TXP multi-chassis routing platform and bring up/validation in the lab.
Designed a fast paced new technology product blade based on Cavium Octeon 3840 chipset (with DDR2 and RLDRAM2 interfaces) deployed in Juniper SRX system.
Designed a high density security processor blade for SRX platform. Also planned and successfully designed the DC-DC VRM subsystem for this blade.
Designed a high density 10Gig/1Gig plug-and-play line card with common base board for SRX platform.
Based on the functional specification, developed, debugged and tested the CPLD Verilog code for successful shipping products.
Closely worked with cross functional teams involving SW, mechanical, power, SI, Diagnosis, Test engineering, Quality Assurance and operations and influenced them towards a common goal of
product success.
Alloptics Inc., Livermore, CA
Principal Hardware Engineer
July 2005 to Dec 2006
Architected and designed chassis based solutions for fiber to home application through PON includes Controller card, Line card, and management card etc.
Designed and developed Security processor module (SPM) with Cavium Network processor (Octeon chipset 3840) for security application. The Network processor interfaces with high speed DDR2 SDRAM and RLDRAM to run DFA (Deterministic Finite Automation) engine.
UTStarcom Inc., Alameda, CA
Senior Hardware Engineer
April 2002 to June 2005
Designed and developed Central controller card and GEPON line card for ATCA Chassis. The central controller card was MPC8560 based design and GEPON line card was MPC8250 based design for fiber to home application with chassis management functionality.
Designed and developed Switch Fabric module for voice over IP (VoIP) application in COMPAC PCI chassis using MPC8245/MPC8250, Marvell Switch Fabric (98EX120) and Marvell Gigabit Ethernet Phy. This module supported 24 GE ports for data & voice application.
Premisys/Zhone Technologies Inc., Oakland, CA
Senior Hardware Engineer
February 1999 to March 2002
Designed and developed 24 ports G.SHDSL, ADSL, POTS line card for Multiple Access Local Concentrator, Broadband Access Network
24 ports G.SHDSL using MPC8260, LUCENT APC controller, GLOBESPAN G.SHDSL chipsets and proprietary FPGA for backplane communication.
24 ports ADSL linecard using MPC8260, LUCENT APC controller, TI ADSL chipsets and proprietary FPGA used for backplane communication.
24 port POTS card using MPC850, ST microelectronics codec and SLIC along with TI DSP for silence suppression for TDM to ATM application (AAL2 layer).
Designed and developed Voice over ATM gateway including GR303 trunking interface
This card is a plug in module for TDM access platform which allows interworking between an ATM network with GR-303 grooming capability. The upstream from VTOA board is TDM link connected to CLASS 5 switch, while downstream form the VTOA board is an ATM link connected to the user’s telephones via ATM IAD.
This blade used MPC860 SAR, TI 6202 5409 for echo cancellation and silence suppression, LUCENT TSI ( 32 port both voice and signaling cross connect ), UTOPIA FPGA ( FLEX 10K30), GLUE CPLD,DPRAM for backplane interface and TDM to ATM formetter FPGA both in transmit and receive direction .
Provides IP connectivity for internet access and ability to route IP packets between LAN (Ethernet 10 Base T) and WAN (T1) port. A V.35 port for connecting the router and optional DSX_1 port to connect a PBX are also supported and offer transparent data transfer.
This product used a MPC860 processor, one FPGA for signaling and voice integrity, COMET T1/E1 framer and glue logic interface.
Education:
MASTER OF TECHNOLOGY in Electronics and Communication
Institute of Radio Physics and Electronics
Calcutta University, INDIA
BACHELOR OF TECHNOLOGY in Electronics and Communication
Institute of Radio Physics and Electronics
Calcutta University, INDIA
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