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Analog IC Design Engineer

Fremont, California, United States
February 08, 2018

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***** **** ****** ******, *******,CA-94555



Professionally focused Electrical Engineer competent in Analog/Mixed-Signal Circuit Design/ debugging aiming to obtain an opportunity in the field of VLSI

• Excellent communication skills, team player.

• Expert knowledge in DRAM, Non-Volatile Memory (NVM) Design, Delta Sigma ADC, DAC, PLL, LPDDRs, Op-Amps (FDA), Voltage regulators (LDOs).

• Management of small team of Engineers in Analog/mixed signal circuit Design. EDUCATION

Master of Science in Electrical Engineering (MSEE) Wright State University, Dayton, Ohio. Cumulative GPA: 3.6/4.0 Bachelors of Technology in Electronics and Communications (BSEE) Krishna University, Andhra Pradesh, India. Cumulative GPA: 3.8/4.0 COURSEWORK

CMOS Radio Frequency & Mixed Signal IC Design RF Power Amplifiers VLSI Design, Synthesis, and Optimization Fundamentals of CMOS VLSI VHDL Programming & FPGA Design Advanced CMOS VLSI Computer Networking VLSI Testing and Design for Testability. WORK EXPERIENCE

CO-OP/ Graduate Research Assistant at Wright State University. 3 years hands-on experience in Analog IC design from 500nm to 90nm process nodes with decent knowledge on technology scaling effects. Experience in RTL coding to GDSII flow in Digital design and experience with EDA tools used for Digital Simulation, Synthesis, Placement and Optimization. CO-OP/ Thesis: 8-bit Successive Approximation Pipe-lined Analog to Digital Converter (SAP-ADC) Worked extensively on designing a high speed and accurate 8-bit SAP-ADC with self-calibration in IBM 90nm CMOS technology. This unique pipelined design has a conversion rate equal to clock frequency and it implements the successive approximation algorithm using parallelism and Pipelining. This is crafted in such a way that the design eliminates the need for residue circuits (HF analog subtract and multiply) which are common in traditional Pipelined ADCs. The design was implemented in CADENCE and the performance was analyzed using the Cadence ADE environment. Simulations were performed with 1GSPS clock and 125 MHz input. From the FFT of the 8-bit output the SFDR achieved is 52.53dB and the figure of merit (FOM) is 65.52fJ/conversion. Independent Research: Co-simulation between CADENCE and MATLAB/Simulink using Verilog-AMS simulator Worked on Co-simulation between CADENCE and MATLAB/Simulink using Verilog-AMS simulator in CADENCE and verified the work with a simple CMOS Inverter circuit. This work was documented and later used in my research on ADCs extensively. Graduate Teaching Assistant at Wright State University. Lab experience: Duties include but are not confined to assisting students in the design of various Analog to Digital(ADC), Digital to Analog Converters(DAC), Bandgap references(BGR), Phase Locked Loop(PLL) and Voltage regulators in Cadence using TSMC 180nm CMOS technology. SKILLS

CAD Tools: Cadence VIRTUOSO 6.1.5 Layout and Schematic Editor RTL compiler SOC Encounter NC Sim SPICE SIMVISION Xilinx ISE MATLAB/Simulink Programming Languages: Shell scripting/LINUX C C++ Verilog VHDL System-Verilog Perl. Operating Systems: Linux Windows (MS Office, Excel Mac OS. Test Equipment: Oscilloscopes Signal/Function Generator Multimeter Network Analyzer. CORE COMPETENCIES

• Very good in RTL coding ASIC design flow Digital logic design Timing Closure (CTS) Static timing analysis Place and Route FPGA mapping in XILINX.

• CMOS Schematic design of A/D, D/A, SMPS, DC-DC converters (Buck-Boost), Embedded C coding using ARM Cortex-M4F,

• Designing layouts in Virtuoso XL (LVS/DRC), deep knowledge on semiconductor device physics, submicron technologies, PVT variations, Noise/mismatch analysis.

• Decent knowledge in PCB design using EDA tools like Altium and OrCAD/Allegro and embedded communication protocols (USB, SPI, I2C, UART) PUBLICATIONS

• Kotti, Vivek. "Design of an 8-bit Successive Approximation Pipelined Analog to Digital Converter (SAP-ADC) in 90 nm CMOS." Electronic Thesis or Dissertation. Wright State University, 2017. OhioLINK Electronic Theses and Dissertations Center.

• Published a research paper titled “Efficient allocation of power resource in OFDMA systems using diverse modulation techniques” in an International journal named IJAREEIE (volume 3, issue 4, April 2014).


High speed Sample and Hold Buffer circuit in IBM 90nm CMOS.

• Successfully implemented high speed Track and Hold circuit with switching frequencies up to 2GHz.

• The design optimized to achieve an error voltage of less than 1mV.

• This switch designed in CADENCE was later used in my dissertation of 8-bit SAP-ADC. High speed Regenerative Latch based Comparator in IBM 90nm CMOS.

• This design uses features from both open loop and regenerative approaches to achieve high resolutions without sacrificing speed.

• The widths of all transistors have been optimized while maintaining minimum length on all of them to achieve a delay of 300 ps.

• The minimum resolvable voltage 1 mV and speed up to 1.5 GHz is achieved with this optimized design. Implementation of Circular buffer array in IBM 90nm CMOS using Time Interleaving.

• Array of 8 successive sampled and held sine waves each separated by precisely 1 clock period has been achieved.

• The Circular Buffer is implemented using a cascade of a Pulse generator and 10 to 8 Analog switching Matrix.

• This design eliminates the adding up of errors from previous T/H stages in the case of serial T/H buffer circuit. Synthesis of 16-bit adder (RTL to GDS ASIC Design Flow).

• 16-bit adder and multiplier with all 3 architectures was designed, simulated and synthesized using Cadence RTL Behavior synthesis tool. Mapped to layout using Cadence RTL compiler and Encounter tools.

• Placement and routing was done in such a way to optimize the PDA product. 16- bit sequence detector using Moore and Mealy FSMs.

• This project helped me understand Xilinx Virtex6 FPGA.

• Designed FSMs in VHDL, verified functionality in Xilinx ISE design suite and then mapped the design to Virtex6 FPGA.

• The o/p is read through LCD interface on the kit. 4- bit Flash ADC (IBM 90nm).

• A 4-bit Flash ADC for 1MHz input and 100MHz clock was designed in CADENCE schematic editor using IBM 90nm technology.

• Its performance was analyzed performing DFT power and transient analyses.

• Effect of increasing the clock up to 2GHz was observed.

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