Verilog, System Verilog, SV Assertions, Physical Design, DFT

MANJUNATH EKANATH GUNAGI

*** ***** ******, *#***, Campbell, CA – 95008 Email: ********.**@*****.*** Phone: 937-***-**** OBJECTIVE

Seeking an entry level full-time opportunity in the field of FPGA/ASIC Design and Verification, Physical Design, DFT. SKILLS

• Programming Languages : Proficiency Level

Verilog, C :

System Verilog, System Verilog Assertions:

VHDL, PERL :

Linux Shell Scripting, X86 Assembly :

• Verification Methodologies: UVM

• Design Tools: Cadence Virtuoso, Cadence NC Launch, Xilinx ISE 14.1, Xilinx Vivado, ModelSim, Microwind, Questasim, Synopsys Galaxy Custom Designer(32nm), Synopsys Tetramax, Synopsys Design Compiler, Synopsys VCS, Quartus Prime, Cadence Encounter, Primetime, IC Compiler, Chipscope Pro

• Protocols: AMBA (AHB), I2C

PROFESSIONAL EXPERIENCE

Qcentum Technologies LLC, Texas, US Software Analyst Aug’17 - Present

• Good knowledge on Bigdata eco systems such as Hadoop HDFS and Map Reduce, Hive, Sqoop, Hadoop Streaming, Apache Spark and databases like SQL, ORACLE.

CoreEL Technologies, Bangalore, India Intern Aug’12-Jan’13

• Verification of I2C bus using System Verilog – ASIC Verification o Developed the system Verilog verification environment which involves generator, driver, scoreboard, monitor, interface. o Constraint random verification was used to generate the test cases and functional coverage and Code Coverage was also checked.

• Data Acquisition Controller for ADC 0808

o Involves finite state machine to design the necessary control logic for the ADC0808 using Verilog and simulation using Modelsim.

• Design and Verification of Frame Detector

o Designed the frame detector using finite state machine which detects 3 consecutive frames each of 20 bits having “1010” header pattern and 16-bits data and verified the design using Verilog test bench using Xilinx ISE

• Design of Round Robin Scheduler

o Designed the round robin scheduler using Verilog, deals with 8 requests and generated grants based on the round robin priority. ACADEMIC AND RESEARCH EXPERIENCE

Wright State University, Ohio, USA Graduate Student Sept’15-Apr’17

• Low Power Design of 64-bit Full Adder with Carry-Skip using 32nm technology o Designed the schematic for 64-bit Full Adder with low power techniques, which aims at delivering low area and good speed. o Involves the use of pass transistors for low power and transmission gate to prevent the signal degradation.

• 6X6 Booth multiplier

o Designed and simulated the low power model of 6x6 Booth multiplier using Cadence Virtuoso.

• Development of an Embedded system

o Involves RTL design for FPGA which collects data from 3D accelerometer and stores it in circular buffer which involves use of IP core. o It requires programming the Arduino using embedded C, which collects data from FPGA and then sends data to the PC which will be displayed on PC using MATLAB. Involves FPGA simulation using do file

• ATPG for 16-bit ALU

o Designing the 16-bit ALU using Verilog and performing ATPG, targeting stuck-at-fault models to determine the fault coverage. o Performing functional verification, finding critical path and estimating the power, delay, area(PDA). o Good knowledge on DFT Scan Insertion, Scan Compression, MBIST, JTAG, Fault modelling (Stuck-at, Transition, Path Delay)., Boundary Scan, Lock up latch, clock gating.

• 16-point Butterfly Fast Fourier Transform(FFT) – FPGA flow o Designed 16-point FFT using structural model in VHDL, did verification and simulation on sub-system and chip level using Xilinx ISE, synthesised with pin constraints, implemented on Xilinx Vertex 6 which displays the maximum bin number on the FPGS display.

• 16-point Butterfly Fast Fourier Transform (FFT) – Complete ASIC Flow o Designed 16-point FFT using VHDL, simulated using Cadence ncsim, synthesised the RTL design to gate level using Cadence RTL Compiler in LINUX environment using TCL.

o Synthesized circuit all the way to layout using Cadence Encounter, which involves floor planning, power planning, routing, placement, clock tree synthesis, and did the power, area and timing analysis.

• Designed 16-Bit Arithmetic Logic Unit using 32nm technology – Digital Full Custom VLSI Design o Designed the CMOS transistor level schematic and layout of full custom 16-bit Arithmetic Logic Unit which includes logic design for Arithmetic Extender and Logical Extender, performs 4 arithmetic and 4 logical operations using Synopsys Galaxy Custom Designer. o Performed Design Rule Check (DRC), Layout Verses Schematic (LVS), Layout Parasitic Extraction (LPE), simulation, and calculated Power Analysis, Delay and Area(PDA).

ACADEMICS

• M.S. (Electrical Engineering) GPA- 3.7/4 Fall’15-Spring’17 Wright State University, Ohio, US

• B.E. (Electronics and Communication Engineering) GPA-3.09/4 Sep’08 – Jun ‘12 Visvesvaraya Technological University, India

RELEVANT COURSEWORK

Low Power VLSI Design, VLSI Synthesis and Optimization, VLSI Testing and Design for Testability (DFT), Digital Circuit Design Using FPGA, Very Large Scale Integrated Circuit Design(CMOS), Embedded Systems, DSP.

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