Verilog, Perl, Digital IC design, FPGA/ASIC design, Physical Design

Jiajia Wang

bonnet Ct, San Jose, CA***** ************@*****.*** 972-***-****

OBJECTIVE

Seeking for Fulltime employment in the field of IC design, ASIC design, SRAM design and FPGA design stating immediately EDUCATION

• M.S, University of Texas at Dallas (UTD), Research Assistant Sep. 2014 – Feb. 2018 GPA: 3.87/4.0, Electrical Engineering

• B.S., Saint Louis University (SLU) Feb. 2012 – Dec. 2013 GPA: 3.71/4.0(Magna Cum Laude), Electrical Engineering (accredited by ABET)

• Diploma., Nanyang Polytechnic Singapore (NYP) Mar. 2008 – Mar. 2011 GPA: 3.72/4.0, Electronic, Computer and Communication(ECC) SKILLS

• Solid background on frontend and backend digital circuit design, 6-T cell SRAM design and FPGA design

• Programming Language: C, Perl, TCL, Verilog

• Software Package: Xilinx ISE, MATLAB

• EDA Tools: Synopsys – HSpice, PrimeTime, Design Compiler, IC compiler, VCS, Custom Compiler, ESP-CV Cadence – Virtuoso Schematic and Layout editor, Encounter, Conformal, Innovus Mentor – Modelsim, Calibre

• Operating System: Linux, Unix

• Good communication, writing, analytical and problem-solving skills WORK EXPERIENCE

Digital IC Design Researcher Intern, MediaTek Austin May. 2017 – Dec. 2017

• Designed and implemented customized 6T cell SRAM with 2.5GHz working frequency using TSMC 7nm; Simulated design using XA to verify the functionality and timing of the SRAM; Went through the SRAM CAD flow of Synopsys ESP-CV equivalent and redundancy check as well as the Totem EMIR post layout check

• Developed a tool using Verilog and Perl script that can prototype an area efficient on-chip programmable unit on which the user can program designs after tape out. The programmable unit constructed with SRAM blocks which possess FPGA features but occupies less area on-chip. The tool prototypes the mapping process by automatically synthesizing an input RTL design and using Min. cut algorithm to partition the design into small pieces then map into the FPGA-like programmable unit.

Research Assistant, Nanometer Design Laboratory of UT Dallas Sep. 2014 – May. 2017

• Implemented a novel Field Programmable Transistor Array (FPTA) in GF65n; in charge of the CAD flow including library characterization, design synthesis, placement & route, and static timing analysis with implemented novel algorithm. VLSI Teaching Assistant, UT Dallas Sep. 2015 – May. 2017

• Tutoring students with VLSI Design lectures and term projects; Assisting them with resolving course problems Assistant Engineer, JVC Electronic Singapore Pte. Ltd April. 2011 – Feb. 2012

• Checked PCB design against specifications; Tested PCB functionality and resolved process issues. Associate Engineer Internship, Institute of Microelectronics, Singapore Mar. 2010 – Jun. 2010

• Fabricated the RF Micro Electromechanical Systems (MEMS) resonators to enhance the system integration level significantly, achieved lower power consumption with better signal integrity RESEARCH/PROJECTS

Nanometer Design Laboratory, as Research Assistant of UT Dallas 2014 – 2017 A Field Programmable Transistor Array (FPTA) Featuring Single-Cycle Partial/Full Dynamic Reconfiguration

• A novel CMOS computational fabric named FPTA was designed and developed in GF65nm technology

• The FPTA consists of carefully arranged transistors which can be configured to implement a target digital circuit

• An ability to dynamically switch among three configurations that are simultaneously stored was implemented

• Hierarchically arranged, high throughput, asynchronous pipelined memory buffers were designed to support rapid partial or full modification of a stored configuration Nanometer Design Laboratory, as Research Assistant of UT Dallas 2016 - 2017 Static Timing Analysis Model for Pass Transistors

• Implemented a high accuracy (1% error compare to Hspice simulation), memory efficient, multicore and multithreading supported STA model

• The implemented algorithm is capable to work on both ASIC and special customized fabric which beyond the limitation of Primetime on transistor model

Nanometer Design Laboratory, as Research Assistant of UT Dallas 2015 Standard Cell Library Characterization with Power and Delay Optimization

• A library with 24 basic standard cells and 234 expended compound cells was characterized using Siliconsmart ACE

• Carefully designed and studied each of the cell in the library for power, area, and delay optimization Department of EE, University of Texas at Dallas 2014 32 bits Multiplier design from RTL to Post Layout Verification

• A RTL of 32-bit multiplier using Verilog was designed and synthesized to a 6000-cell structural circuit

• Standard cells were designed, laid out and characterized in IBM 130nm using Cadence Virtuoso and Siliconsmart Performed DRC, LVS check and functional simulations

• Auto placed and routed the design using Encounter; Analyzed the timing and power of the design using Primetime Department of EE, University of Texas at Dallas 2014 ASIC Design of Low Power Mini Stereo Audio Processor

• RTL design of the digital FIR filter algorithm based on Power of Two coefficients to achieve ultra-low power low cost

• Placement, clock tree synthesis and routing with SMIC 180nm library using IC Compile

• Post layout simulation and Primetime STA to resolve setup and hold violation PUBLICATION

A Field Programmable Transistor Array Featuring Single-Cycle Partial/Full Dynamic Reconfiguration, Jingxiang Tian, Gaurav Rajavendra Reddy, Jiajia Wang, William Swartz, Yiorgos Makris, Carl Sechen, Automation and Test in Europe(DATE), 2017 GRADUATE COURSES

VLSI Design ( Dr. Carl Sechen )

Advanced VLSI (Dr. Carl Sechen)

ASIC Design (Dr. Dian Zhou)

Special Topic in Hardware Security (Dr. Georgios Makris) Computer Architecture (Dr. Georgios Makris)

Advanced Digital Logic (Dr. William Swarz)

Analog Integrated Circuit Design (Dr. Hoi Lee)

Linear System (Nicholas Gans)

AWARDS AND PROFESSIONAL AFFILIATIONS

• Research Assistantship, UT Dallas 2015-2016

• Dean’s Honors list, Saint Louis University 2012-2013

• Tau Beta Pi - National Engineering Honor Society 2013

• Jesuit transfer scholarship, Saint Louis University 2011-2013

• Admitted to Director list for outstanding Academic Performance 2008-2011

• First place position violinist in the Symphonic Band Category at the SCL International Youth 2009

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