Engineer Professional Experience

SUGANDHA SHARMA ********.********@*****.***

San Jose, CA 95134 352-***-****

Summary of Skills

• Hands on experience with EDA tools Cadence Virtuoso (Schematic and Layout)

• Proficient in analog circuit simulators Spectre and SPICE

• Experience in Verilog and Python scripting

• Familiar with Linux/Unix environments

• Comprehensive knowledge of transistor level analog design flow

• Extensive knowledge of MOSFETs, operational amplifiers, current mirrors and switched capacitor circuits

• Strong leadership, troubleshooting and communication skills PROFESSIONAL EXPERIENCE

Application Engineer – Analog-Mixed Signal Simulator June 2016 – May 2017 Mentor Graphics Corporation, Fremont, CA

• Debugged DC operating point convergence issue to deliver promised performance and accuracy for Analog FastSpice (AFS) simulator.

• Resolved AFS simulator compatibility exception with SPICE and Spectre syntaxes; providing efficient bug resolution by developing netlists to reproduce the bug in the absence of customer provided test case.

• Foundry qualified AFS simulator, for a semiconductor design company, on TSMC BCD 0.15um by running test suites at TSMC San Jose.

• Tested and verified enhancements in accuracy and performance by executing regression test suites. EDUCATION

Master of Science in Electrical and Computer Engineering May 2016 University of Florida, Gainesville, FL

Coursework: CMOS VLSI Design and Technology, Analog IC Design, Mixed Signal IC Testing, Reconfigurable Computing, Computer Architecture, Automated HW/SW Verification Bachelor of Technology in Electronics and Communication Engineering May 2014 Punjab Technical University, India

ACADEMIC PROJECTS

Design of a Switched Capacitor Circuit using Telescopic opamp Technology Used: Cadence Virtuoso

• Designed a telescopic opamp with CMFB and biasing circuitry, meeting the required gain, bandwidth and phase margin.

• Developed a low power and low gain error switched capacitor circuit using the designed opamp.

• Implemented the layout of the circuit, floorplan optimized for area. Digital Backend of High Speed ADC

Technology Used: Cadence Virtuoso, Cadence Encounter, Verilog

• Designed an ADC digital backend in 250 nm CMOS technology to run at a speed of 4GHz with resolution of 5 bits.

• Generated bubble error corrector and encoder using Verilog and Cadence Encounter for place and route.

• Custom designed the DEMUX at input using CMOS logic to down-sample the 4GHz input to 500MHz. Design of SRAM

Technology Used: Cadence Virtuoso

• Designed a 4 bit 4x1 6T SRAM in 250nm technology with driver and sense amplifier, row decoder and column.

• Created the Schematic & Layout using Spectre & Cadence Virtuoso respectively.

• Evaluated the parameters such as hold, read and write stability and noise margin, and ran LVS and DRC checks.

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