Electrical Engineer Engineering

JIMISH DODIA

****, ******** ******, *** **** https://www.linkedin.com/in/jimishdodia ***********@*****.*** San Jose, 95126 +1-669-***-****

CAREER SUMMARY

• Electrical Engineer with an experience of 2 years. Master’s Graduate in Electrical Engineering specializing in Digital VLSI Design

• Comprehensive knowledge of Electrical Engineering, PC Board Design, troubleshooting Electronic Circuits, transistor level circuit design (CMOS) & writing RTL & Gate level codes. Thorough knowledge of EDA tools and complex design methodology.

• Writing & modifying Python scripts. Adept at static timing analysis and in-depth understanding of circuit simulation tool.

• Quick learner with excellent problem-solving and documentation skills, good communication, multitasking & interpersonal skills WORK EXPERIENCE

Lunera Lighting, Inc. AUGUST 2017 – JANUARY 2018 Electrical Engineer

• Hardware design, prototyping & debugging of company’s IoT based Smart T8 lamp with BLE and Wi-Fi functionality. The team drove product to pass FCC, UL & DLC compliance. Also, responsible for automating commissioning, and flashing firmware on sensor board.

• Was responsible for development of a test plan to ensure high quality throughput of the product. The test plan successfully tested the overall assembly, functionality and Dashboard website to control the Smart T8 Lamp.

• Conducted thermal testing on various products using Thermocouples and Data Logger.

• Started reliability testing for all products of the company, keeping a track of the degradation of the components over time. Stack Labs, Inc. acquired by Philips AUGUST 2016 – AUGUST 2017 Electrical Engineer

• Hardware & software debugging using Python and Linux CLI. Conducted tests as required to validate performance within target specs, including bench tests, technical documentation, opto-electronic tests, RF tests.

• Built Python scripts to automate testing steps to qualify products as good to be shipped. Responsible for bench-testing & integrating RF sensors, micro-controllers & ZigBee communication into bulbs.

• Developed multi-layer PCB net list, schematic and layout for Mockup ZigBee Hub using Altium Designer 17 to support company’s IoT-based responsive smart lighting technology.

• Coordinated between hardware and firmware departments, as well as component vendors and PCB design software providers. Scalable Systems Research Labs, Inc. MAY 2016 – AUGUST 2016 ASIC Design Engineer

• Designed a memory controller interface between SDRAM and AMBA AHB bus Interface. EDUCATION

Masters of Science in Electrical Engineering San Jose State University, CA AUGUST 2014 - MAY 2016 Bachelors of Engineering in Electronics & Telecommunications University of Mumbai, INDIA AUGUST 2009 - MAY 2013 TECHNICAL SKILLS

Programming Languages: Python Scripting, UNIX, Linux CLI. Board Design: Schematic capture, library management, footprint and symbol creation, Multi-layer dense surface mounts and through hole boards layout, Bill of materials (BOM), engineering change orders (ECOs), Gerber data. EDA Tools: Cadence Virtuoso, Synopsys VCS, Synopsys Design Compiler, Altium Designer 17, AutoCAD, Xilinx Vivado, Xilinx ISE. Hardware Descriptive Languages: Verilog HDL, System Verilog. Others: RTL Design using Verilog, Debug, Power Supply, Logic Analyzer, Oscilloscope, DMM, soldering rework of SMT. PROJECTS

• Implementation of Advanced High-performance Bus based DDR SDRAM Memory Controller Soft Core APRIL 2016 Designed the memory controller using Verilog. Design passed RTL and Gate Level Simulation using Design Compiler and NC Verilog. Memory controller is scalable so the user can select bus width of data, address to which the controller automatically adjusts FIFO size

& depth. Synthesis script was written effectively to meet timing of the hardware for Toshiba, TSMC and AMI libraries.

• Time to Digital Converter (TDC) using Vernier Line Delay implementation using Cadence Virtuoso and Assura MARCH 2015 Designed schematic for Linear 1-stage Vernier Delay Line implementation for TDC with operating Frequency of 5GHz(45nm technology) Performed corner analysis and proved that the design is process (SS, FF, and TT) independent. Standard cell design and layout performed. PVT, DRC, LVS, and RCX Analysis also performed successfully.

• 4-Bit up/down synchronous counter with asynchronous reset FEBRUARY 2015 Designed schematic and physical layout of the design using 45nm Toshiba Technology at 333 MHz with corner analysis, clean DRC/LVS on Cadence Virtuoso.

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