Mr. VIRAL B. TANDEL

*** ***** **** ***, ******** CA, 95035 Email: ac4g5l@r.postjobfree.com Ph No: 669-***-**** OBJECTIVE:

Electrical Engineer specialized in VLSI/ASIC logic design, seeking an Full time position. QUALIFICATION SUMMARY:

3 4 Strong understanding of gate, transistor and circuit level design and verification. 3 4 Knowledge of analog and mixed signal design methodologies. 3 4 Strong understanding of digital system design, simulation and synthesis. 3 4 Worked on ASIC based design using Verilog.

3 4 Hands on experience of HW design tools ( LTspice, OrCAD, Ultium Designer) 3 4 Good debugging skills.

3 4 Ability to learn new technologies, team player, goal-oriented and highly motivated. 3 4 Excellent Communication and Organization skills. EDUCATION:

MS Electrical Engineering, Northwestern Polytechnic University. CGPA: 3.91 (May 2017) BE Electrical Engineering, Uka Tarsadia University, India. 1st Class (June 2015) RELEVANT COURSES:

Microelectronics Circuit Design, Digital Design and HDL, Advance Timing Analysis, VLSI Design (Place and Route), Advanced FPGA Design, Advanced Analog IC Design, Systems Analysis and Simulations, Advanced Digital IC Design, Design Verification with SV. SKILLS:

3 4 Hardware Description Language: Verilog

3 4 Scripting/ Programming Languages: TCL, C(basic), Unix(basic) 3 4 Simulation Tools: Modelsim, Xilinx ISE, MATLAB, Cadence, LTspice. 3 4 Tools/Packages: Synopsys

3 4 Platform: Windows, MacOS

3 4 Timing Analysis Tool: Prime Time

3 4 VLSI (Tools/Flow): IC Manufacturing flow, SCAN tests, ATPG, BIST 3 4 PCB Design tools OrCAD Capture, Altium Designer, L-EDIT 3 4 Lab Equipment: Logic Analyzer, Oscilloscope, DMMs. ACADEMIC PROJECTS:

3 4 Design of SRAM Memory

Worked with team of two to design 8K SRAM memory block. 1x8k memory to perform to 8 bit read/write at a time. The design was implemented for 1V voltage domain. Column and Raw address decoders, read/write buffer were designed to achieve optimum timing and signal quality. The design was developed and simulated using Spice.

3 4 DC - DC Buck converter

Designed a DC-DC Buck (step-down) converter to support 12 V to 6.6V step down operation using PWM technique. This converter was simulated to support 35V of breakdown voltage as well as load capacitance of 1000uF for 10A load current.

3 4 Design and implementation of Synchronous FIFO

Designed 4 bit synchronous FIFO with address depth of 64. The design was developed using Verilog HDL and simulated using Xilinx ISE design platform. Design was simulated, synthesized and programming file was generated. Complete design was verified using Digilent NEXSYS2 FPGA Platform.

3 4 PCB design of Embedded system

Implemented design for embedded system using 24 pin mixed signal microcontroller MSP430AFE2x3. Design contained ports for RX/TX as well as test points for all the key signal in addition to LED indicators for power and flags. This design (schematic and layout) was implemented using Altium designer as a part of coursework for VLSI design (place and route). Reference: Available upon request.

Note: No Visa sponsorships required.