| Resume alert | Resumes 51 - 60 of 387 |
Sholeh Gregory Technical Writer Security
Livermore, CA
... Altera Corporation, San Jose, CA 12/04 – 1/05 Contract Senior Technical Writer, Engineering Division Increased the usability of an application note about a design security feature embedded into an FPGA device, which decrypted a configuration bit ... - 2020 Oct 31
... Altera Corporation, San Jose, CA 12/04 – 1/05 Contract Senior Technical Writer, Engineering Division Increased the usability of an application note about a design security feature embedded into an FPGA device, which decrypted a configuration bit ... - 2020 Oct 31
Sr. Electrical Engineer Design
Campbell, CA
... Extensive expertise across the span of ASIC, FPGA, board and system level design disciplines. Debugging and EDVT test of Cadence Z1 product, Klingon products and VolcanP products. Debugging and test of 100Gbps Ethernet CISCO products. Design and ... - 2020 Oct 23
... Extensive expertise across the span of ASIC, FPGA, board and system level design disciplines. Debugging and EDVT test of Cadence Z1 product, Klingon products and VolcanP products. Debugging and test of 100Gbps Ethernet CISCO products. Design and ... - 2020 Oct 23
Design Engineer Engineering
Los Gatos, CA
... •Built FPGA validation environment with single FPGA board, responsibility includes bit file compilation, programming FPGA, and board level debug for functionality accuracy. •Constructed FPGA & bring up test plans. Executed FPGA validation on new and ... - 2020 Oct 06
... •Built FPGA validation environment with single FPGA board, responsibility includes bit file compilation, programming FPGA, and board level debug for functionality accuracy. •Constructed FPGA & bring up test plans. Executed FPGA validation on new and ... - 2020 Oct 06
Principle System Enginner
San Jose, CA
... Experience in Platform development, Datacom SW development [Control plane and data plane], Board Bring-up, Boot-loader/BSP, Embedded SW/Firmware, Different Hardware devices and ASICs/PHY bring-up, Interface bring-up, FPGA drivers, ASICS drivers ... - 2020 Sep 22
... Experience in Platform development, Datacom SW development [Control plane and data plane], Board Bring-up, Boot-loader/BSP, Embedded SW/Firmware, Different Hardware devices and ASICs/PHY bring-up, Interface bring-up, FPGA drivers, ASICS drivers ... - 2020 Sep 22
Employee Relations Social Media
Scotts Valley, CA
... C, C++, Networks, Routers, VOIP, RF, Wi-Fi, Bluetooth, CPU Architecture, IT, DSP/Mixed Signal, ASIC/FPGA, Ethernet, PC Architecture, Multi-Media & Streaming Video, Optical storage, Adobe, Acrobat, Assembler, E-Commerce, Flat Panel Display. ... - 2020 Aug 11
... C, C++, Networks, Routers, VOIP, RF, Wi-Fi, Bluetooth, CPU Architecture, IT, DSP/Mixed Signal, ASIC/FPGA, Ethernet, PC Architecture, Multi-Media & Streaming Video, Optical storage, Adobe, Acrobat, Assembler, E-Commerce, Flat Panel Display. ... - 2020 Aug 11
Engineer
San Jose, CA, 95135
... 7 FPGA, DDR, En/decoders, ADC/DAC in C/T/FDMA, 3/4G, CPRI WiMAX/GSM/LTE, and etc. • Performed PLL, OSC, LNA/PA, n-QAM/EVM, Mixers, Mux/Demux, S-parameters, BER, EVM, SNR/SINAD, NF, Sensitivity, 1dB, OIP3/5, EMI and etc. • Developed code and drivers ... - 2020 Aug 05
... 7 FPGA, DDR, En/decoders, ADC/DAC in C/T/FDMA, 3/4G, CPRI WiMAX/GSM/LTE, and etc. • Performed PLL, OSC, LNA/PA, n-QAM/EVM, Mixers, Mux/Demux, S-parameters, BER, EVM, SNR/SINAD, NF, Sensitivity, 1dB, OIP3/5, EMI and etc. • Developed code and drivers ... - 2020 Aug 05
Electrical Engineer Design
Santa Clara, CA
... Verification Methods IC Design Technologies Engineering Concept UVM, OVM, VMM Mixed Signal Design Amplifier Design Functional Verification Physical Design Op-Amp design DFT and LVS SRAM Design Electrical Circuit Design Silicon Debugging FPGA ... - 2020 Jul 06
... Verification Methods IC Design Technologies Engineering Concept UVM, OVM, VMM Mixed Signal Design Amplifier Design Functional Verification Physical Design Op-Amp design DFT and LVS SRAM Design Electrical Circuit Design Silicon Debugging FPGA ... - 2020 Jul 06
Electrical Engineer Software
San Jose, CA
... Designed and implemented the circuit that controls elevator system using Xilinx fpga. The hardware used in the project is Digilent Nexys4 board. LINKS https://www.linkedin.com/in/jerrin-mohan-54901226/ - 2020 Jun 01
... Designed and implemented the circuit that controls elevator system using Xilinx fpga. The hardware used in the project is Digilent Nexys4 board. LINKS https://www.linkedin.com/in/jerrin-mohan-54901226/ - 2020 Jun 01
Design Engineering
San Jose, CA
... o Technology-180nm 16 BIT MULTIPLIER USING WALLACE TREE ALGORITHM ON FPGA KIT: (Xilinx Vivado) o Designed RTL code of 16-bit multiplier based on Wallace tree algorithm with half adder and full adder structure. o Implemented on design on Basys-3 Fpga ... - 2020 May 17
... o Technology-180nm 16 BIT MULTIPLIER USING WALLACE TREE ALGORITHM ON FPGA KIT: (Xilinx Vivado) o Designed RTL code of 16-bit multiplier based on Wallace tree algorithm with half adder and full adder structure. o Implemented on design on Basys-3 Fpga ... - 2020 May 17
Marketing Sales
San Jose, CA
... Xilinx (acquirer of Solarflare) - Chief Marketing and Strategy Exec 2019 – Present Data Center Solution Group provider of FPGA, ASIC, Boards and Software accelerator solutions for Networking, Compute (AI, ML, Video...) & Storage: Accountable for ... - 2020 Apr 22
... Xilinx (acquirer of Solarflare) - Chief Marketing and Strategy Exec 2019 – Present Data Center Solution Group provider of FPGA, ASIC, Boards and Software accelerator solutions for Networking, Compute (AI, ML, Video...) & Storage: Accountable for ... - 2020 Apr 22