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Sr. Electrical Engineer Design

Location:
Campbell, CA
Salary:
150000
Posted:
October 23, 2020

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Resume:

Raanan (Ron) Ben-Zur

**** *** ***** **.

Campbell, CA 95008

Tel: 510-***-****

Email: adg8y1@r.postjobfree.com

Professional Objective

Seeking a hardware engineering leader position in a challenging environment.

Experience Summary

Hands on design in the fields of networking, telecommunications, computers, peripherals, and military hardware.

Extensive expertise across the span of ASIC, FPGA, board and system level design disciplines.

Debugging and EDVT test of Cadence Z1 product, Klingon products and VolcanP products.

Debugging and test of 100Gbps Ethernet CISCO products.

Design and development of 10Gbps Ethernet products including network processors and switching devices.

Expertise in Metro SONET Add/Drop Multiplexers, OTN Add/Drop Multiplexers, 10GE traffic.

Design experience with Optical devices, such as 40/80 DWDM, Single Mode laser transmitters, Optical sensors, Optical polarizer, EDFA amplifiers,

More than 5 years design and development of PC level peripherals including graphics and storage controllers.

Development of militarized hardware in the fields of advanced Radars, RPV avionics and flight computers.

Conducted integration testing for complex hardware/ software projects including telecommunications, networking, avionics and variety of computer peripherals, specializing in performance analysis, signal integrity, reliability analysis and standard agencies compliance.

Have successfully taken numerous products from concept to production to market.

Developed code in C, C++, VHDL, and Verilog.

FPGA development using ModelSIM, XILNX tools and Aldec tools.

Project management experience.

Author of 7 US patents.

Work History and accomplishments

Sr. Hardware Engineer Cadence Inc. San Jose Contract (8/2015 – 3/2020)

EDVT of the Target Pod device of the Apollo simulator device.

EDVT of the CCD board device of Apollo.

EDVT of the SCD board device of Apollo.

EDVT of the LD and PLD boards of Apollo.

Schematic design of many of the Paladium products and the daughter boards.

EDVT testing for all Cadence simulation devices.

Verification of multiple board designs related to Z1, Z2, Klingon and VolcanP project.

Assisted in the design of the Protium 4 FPGA board and with testing all its functions.

Sr. Hardware Engineer CISCO Systems Inc. San Jose Contract (06/2013 – 08/2015)

Signal Integrity verification of a 24 port 10GE line card as part of the CISCO router.

Signal Integrity verification of 8 port 100GE line card as part of the Cisco router.

Timing and signal analysis of multiple NP4C and NP5C (Marvell network processors), 4x PQ60 (AMCC 6 port 10GE PHY), multiple CISCO ASICs for memory and network control.

Power analysis using Linear Technology tools and ASICs and MAXIM.

Debugging various CISCO line cards for Field and Manufacturing failures.

FPGA Design Engineer II Intel Inc. Folsom Contract (11/2012- 06/2013)

Memory subsystem design and performance evaluation. Concentrating on DDR2, DDR3 LPDDR2 and LPDDR3.

Design FPGA RTL/ Logic for real-time data collection system. The system is used to collect data for architecture tradeoff studies and memory controller design.

Extensive work with XILINX Virtex6 FPGA using ISE tools including the ISIM simulation tool.

Work with Third parties companies on high performance analog signal amplifiers in order to use board and chip interposers and deal with signal integrity issues.

Wrote functional specs for new boards design by 3rd party company.

Sr. Hardware Engineer Huawei Inc. San Jose Contract (09/2011-08/2012)

FPGA code development for 10G/1G switch and router application based on netFPGA 4 port NIC.

Directed a team of 3 engineers how to design a layer 4 switch including Ethernet, IP, UDP, TCP packets and switching logic.

Implementation is based on Xilinx XC5VTX240T-2FF1759.

Special functions: Bloom filter, 10 different hash functions, Longest Prefix Match (LPM)

Working in centOS linux environment using Verilog, VHDL and Mentor Graphics Questa environment.

Tightly working with netFPGA environment including OpenFlow router.

Sr. Hardware Engineer CISCO Systems Inc. San Jose Contract (03/2011-09/2011)

Signal Integrity verification of a 24 port 10GE line card as part of the CISCO router.

Timing and signal analysis of multiple NP4C (Marvell network processors), 4x PQ60 (AMCC 6 port 10GE PHY), multiple CISCO ASICs for memory and network control.

Power analysis using Linear Technology tools and ASICs.

Sr. Hardware Engineer Taseon Inc. San Jose (08/2007- 03/2011)

Participated in the design of EDFA receive and transmit modules.

Developed in-line 10Gbps OSNR module without high-speed O-E-O conversion.

Developed 3 boards associated with Optical monitoring functions.

Development Included SPARTAN 3A FPGA, ACTEL FPGA, ADI DSP, interface to high speed dual core processor, PCI Express, Signal Integrity using Hyperlynx tool.

Optical components: Enablance proprietary 3x 8ports DWDM switch, Agility, Bookham and Civcom10G transponders, DICON Tunable laser, QWP polarizer, PIN diodes receivers, AXSUN OM3 Optical Monitoring devices.

Sr. Hardware Engineer Rapport Inc., Redwood City (02/2007- 08/2007)

Design and development of two PCI-Express boards with up to four KC1-256 ASICs, High speed search and sort RAM and sophisticated power management to support high speed IOs at 1V, 1.2V, 1.8V, 2.5V and 3.3V. PCI –Express implementation is base on 8 lane Xilinx Virtex-5, XC5VLX110T. KC1-256 is an advanced 256 parallel processors with reconfigurable logic within 1 clock cycle. Familiarity with Xilinx ML555 evaluation card as well as Agilent and VMETRO PCI-Express protocol Analyzers.

Tools used in the development,:

o Mentor Graphics DxDesigner, IODesigner, Hyperlynx and ModelSim.

oXilinx ISE 9.1, and Lattice Power CPLD synthesis and simulation tools.

Sr. Hardware Engineer Intellambda Systems Inc., Fremont (03/2003- 01/2007)

Developed five 10G interface boards for Intellambda’s IL640 system. The design included EZ-Chip’s 10G network processor NP-1C and NP-2C, Switch Fabric Interface and 160 Gbps packet switching chips in addition to Ample’s SONET framer, Motorola’s MPC8270 processor and optical transceivers. Design work included extensive FPGAs/CPLDs development using VHDL, XILINX ISE development tools as well as Emulation Technology’s Model Sim tool.

Debugging and optimizing state of the art 10G network processor traffic destined for DWDM equipment.

Worked closely with software development assisting in development of device drivers, boot-up code, diagnostics and system applications. This work required extensive programming skills and expertise in C and Linux operating system.

Designed advanced 10G FEC and on board switching capability, utilizing Intel and Vitesse 10G components.

Principal Engineer Ciena Corp., San Jose (03/2001-03/2003)

Lead the development of a 160 Gbps cross connect system based on proprietary high-speed ASICs, GR-1244 timing module, MPC8260 embedded controller, proprietary high speed backplane design, FPGA controller and a patented inter boards communication controller.

Conducted integration tests of the Online Edge product, which includes multiple ports of CWDM, ESCON, FC, GBE, FE, OC-48/12/3, SDH- STM1, STM4, STM16, DS3/E3 and DS1/E1.

Evaluated GBICs, SFPs including jitter measurements, eye patterns measurements, temperature sensitivity, phase delay, time delay and attenuation.

Designed, tested and integrated high-speed backplane for Online next generation products.

Performed verification tests to TISSA-2, 40 Gbps cross connect ASIC.

Worked with NEC, TI, Fujitsu, Toshiba and LSI to define 2.5G serdes interfaces.

Project Lead Cyras, Fremont Fremont (Bought by Ciena 3/2001) (09/1999 – 03/2001)

Developed hardware architecture for K2 product. Including Control, Timing and Cross-connect planes.

Led the development of four SONET/SDH cross connect cards for the K2 system.

Led integration of K2 hardware, which consisted of, OC192, OC48, OC3/12, DS3, DS1, GBE and Cross Connect cards.

Developed Tsnet ™ network. Six patents pending.

Contributed to testing and debugging of 2 strategic ASICs: HISSA (high speed backplane serdes) and TISSA (STS-cross connect).

Architected and supervised the development of the K2 timing and synchronization circuits.

Drove all HW and ASIC integration for K2 Metro director. This project involed meeting GR1244 timing specs, up to 6 nodes of K2 systems, resolving system level CRs.

Advisory Design Engineer Tandem, Cupertino CA 1996 - 1999

Participated in a multidisciplinary development of Gigabit Ethernet gateway to Tandem’s SNET SAN. This project entailed new protocol and filtering engines implemented in IBM G12 ASIC technology.

Development of an ATM, Token Ring and Fast Ethernet adapters for Tandem's S7000/S70000 fault tolerant systems. Boards were based on 68060 processor the TIOGA ASIC and Motorola’s QUICC chip.

ASIC and FPGA development utilizing Verilog, Vera, Synopsis as well as other CAE tools.

Contributed to ServerIO protocol optimization, processor selection for Fast Ethernet controller, Gigabit hardware IP filtering and physical interface.

Consultant P-COM INC. Campbell CA 1995

Led development of an Indoor Unit for a DS3 Radio link.

Designed a proprietary framing scheme for multiplexing DS3 data stream with up to 4 DS1 streams utilizing an Altera FPGA using AHDL and MAX+Two design tools.

Designed a DS3 point-to-point communication control board.

Project Manager Hitachi Ltd. Santa Clara, CA 1989 - 1995

Managed an aggressive engineering team of 7 engineers.

Developed Ethernet and FDDI LAN to Hitachi mainframes bridge products.

Developed project planning, schedules and budgets for complex hardware and software projects.

Developed departmental procedures for design, test, and quality assurance.

Provided engineering expertise to new product planning regularly.

Developed diagnostics program, which was used on all hardware platforms.

Participated in the early definition phase of an ATM to fast Ethernet switch product.

Participated in numerous marketing feasibility studies including PPM (Personal Processor Module), ATM, Wireless LANs, Fast Ethernet, Computerized Telephony, FEP (Front End Processor), and mainframe communication.

Standards activities: Actively participated in the following standard committees: FutureBus, SCI bus, ESCON bus, ATM Forum.

Manager of computer systems, Leading System Inc. 1985 - 1989.

Irvine, CA

Defined, Specified and designed flight control hardware.

Designed and developed a militarized computer based on Motorola's 68020 CPU and the VME bus. Developed digital ground station for RPV. The project involved identifying and selecting a third party's frame buffer and data link.

Designed and developed militarized engine computer based on Intel's 8031 micro controller.

Participated in preliminary design of a DSP for radar signal processor, including definition of a high-speed adaptive node processor custom chip.

EDUCATION

California State University Fullerton M.S.E.E. Computer Design

Ben-Gurion University, Beer-Sheva, Israel B.S.E.E.

Patents:

US 6,980,568 Method and apparatus for system clock synchronization

US 6,920,105 Interface Receive for communications among network elements.

US 6,865,148 Method for routing network switching information

US 6,785,766 Method and apparatus for servicing massive interrupt in random access memory (RAM).

US 6,754,174 Interface for communications among network elements

US 6,633,573 Method and apparatus for generating massive interrupt in random access memory (RAM).

US 5,550,570 Packaging and cooling structure for Personal Processor Module.



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