Annika Lee

Bay Area, CA

408-***-**** / adgpz0@r.postjobfree.com

Qualifications

13+ years of solid technical experience throughout multiple ASIC project cycles.

Lead / Project Managed design and verification teams, developed and coordinated project plan, schedule definition, resource analysis, and status-tracking among cross-functional teams.

Familiar with waterfall and agile methodology.

Excellent skills in communication, presentation, organizing, and planning.

Critical thinker with proven analytical, problem-solving & multi-tasking abilities.

Highly-valued team player and leader experience in multi-site and multi-cultures.

Experience

Cisco System – Hardware Engineer – San Jose, CA (3/2013 – current)

Key Responsibilities & Accomplishments:

Verification Engineer, Team Event Organizer

•Program managed regular team building events and Cisco Visit for Taiwanese high school students. Communicated the information with large team, setup requirement and expectations, track schedules.

•Program managed weekly team trainings in technical knowledge area for continuous education at work. Planned weekly topics, communicated and present information to large team, track schedules, and host and work with team members to deliver quality trainings.

•Work with and support cross-functional design teams such as backend/PD team and external vendor to debug and help identify issues that may block the progress and ensure the quality and timely delivery.

•Developed design verification methodology, including establishing key requirements, identifying tools/scripts needed, creating templates and milestones for building methodology, and keeping track of schedules and status of progress.

•Built block level design and verification schedules, tasks, milestones, deliveries, and track status throughout the project phases.

•Designed an enhancement on egress VOQ blocks for switches.

•Verified PLL and reset & power sequence block, VOQ internal modeling, exact match database, and other shared databases.

Advanced Micro Devices, Inc. - Senior Hardware Design Engineer – Sunnyvale, CA (4/2008 – 12/2012)

Key Responsibilities & Accomplishments:

Project Manager

•Led & project managed two functional blocks in the design team.

•Developed block level design tasks, schedules, milestones, and deliverables, and coordinated with cross-functional teams throughout project phases.

•Delivered all tasks and deliverables on schedule, efficiently monitored status and hosted regular team meetings.

•Successfully and correctly spotted potential issues and raised urgent issues to higher management.

•Implemented detailed status tracking system and reports as well as detailed documentation.

Designer/Design lead

•Designed & validated four functional blocks in FCH (south bridge chipset group) – Embedded Controller, Internal Logic Analyzer, Advanced Configuration Power Interface, & Low Pin Count Interface.

•No post-silicon bugs found on new and legacy features in Embedded Controller.

•Designed & implemented memory control logic for RAM and cache, reset sequence design to meet MS AOAC requirement, global timer counter and control logic to transfer internal memory data to external SD card.

•Designed & implemented clock gating sequence, closely worked with the firmware team to be successfully controlled by both hardware and firmware.

•Built FPGA validation environment with single FPGA board, responsibility includes bit file compilation, programming FPGA, and board level debug for functionality accuracy.

•Constructed FPGA & bring up test plans. Executed FPGA validation on new and legacy features. Verified PS2 and Scan Matrix, RAM and cache decoding, external ROM code fetch, firmware instruction code execution, host access, memory R/W, AB traffics, global timer counter accuracy, and data R/W accuracy on external SD flash.

•Created & maintained design specification and detailed reference documents.

•Efficiently implemented & delivered quality ECO (Engineering Change Order) within a tight schedule.

•Debugged non-verified legacy features, constructed detailed test plans, and reviewed legacy tests with DV. Found several bugs on legacy features during the review.

•Supported various front-end/back-end debug team on legacy feature validation, improved debug tool feasibility, QA & customer support team.

Intel Corporation - Component Design Engineer – Folsom, California (6/2006 – 4/2008)

Key Responsibilities & Accomplishments:

•Designed & validated desktop chipset components under North bridge with concentration on clock & power units for both Bearlake & Ironlake projects.

•Executed PLL modeling & clocking logic designs between clock units & display/graphics/memory/CSI interfaces based on circuit schematics.

•Validated power consumption using Watermark and analyzed & constructed data result.

•Developed high performance simulation methodologies including test plan & code construction, checker & tracker development, and coverage points for both unit level and cluster level validation & debug.

•Delivered quality RTL codes using Verilog & synthesis tests using System Verilog for clock/power/pci-express units during final project milestone.

Skills

Project Management – Scheduling, resource planning, status tracking, risk mitigation, coordination between cross-functional teams and multiple/concurrent projects, waterfall/agile methodology, Scrum, Kanban

ASIC Design & Verification – Verilog, System Verilog, UVM

VLSI – Optimizing delays and performance via architecture explorations, layout, and sizing

Validation – Developing & debugging simulation methodologies i.e. test plans, tests, & trackers/checkers for functional RTL

System – FPGA, ASIC system level design and validation, Switches/Routers, 8051 uController, ACPI/LPC

Tools – Jira, Trello, SQL, Perl, Python, Modelsim, Verdi, Perforce, FS2 (Jtag), LabView, TLA, scope

Education

Professional Certificate in Advanced Project Management (9/2009 – 12/2009)

Stanford University – Palo Alto, California

Master of Science in Electrical Engineering – VLSI (6/2006)

University of Southern California – Los Angeles, California

Bachelor of Science in Electrical Engineering Minor: Mathematics (3/2004)

University of Washington – Seattle, Washington

Industrial Engineering and Management (6/2000)

National Taipei University of Technology (NTUT) – Taipei, Taiwan

Contact this candidate