PETER NGUYEN

**** ****** ** *** ****, CA *****

408-***-****

Email: ade324@r.postjobfree.com

Objective To obtain a Staff or other Design Engineering position. Technical Project Skills

• Projects on designs PCB and tests of circuit boards of Cable/Wireless Digital Transceivers include ISE Navigators, Modelsim, Vxworks, DSP/Xilinx V6/Zyn. 7 FPGA, DDR, En/decoders, ADC/DAC in C/T/FDMA, 3/4G, CPRI WiMAX/GSM/LTE, and etc.

• Performed PLL, OSC, LNA/PA, n-QAM/EVM, Mixers, Mux/Demux, S-parameters, BER, EVM, SNR/SINAD, NF, Sensitivity, 1dB, OIP3/5, EMI and etc.

• Developed code and drivers in Matlab, NI Labview/Teststand/CVI, Pythons, C/C++ VB.

• Familiar with NI modules (MUX, DAQ, DIO and etc.) and Agilent such as VSA, Gen and Spectrum 4440E, VNA 5062A for testing cycles include GPIO, RS232, RS485, LAN IP, IPV6/V4, 802.3 and 802.11

(SAP/TCP/UDP L1-4 protocols) and more.

• Experience in management people in labs, design/test projects, manufacturing floor, customers, and all other issues solving problems.

History

Mattson Technology, Fremont, CA 1/2018- 7/27/20

Staff Engineer in Plasma Design Group:

• Designed interface boards for Wafer Etch/Strip machines using Xilinx Vivado and Cadence tools.

• Performed Etch/Trip wafer machines include RF Gen Chambers, power cables, block drawings, rotors, pumps, mechatronics devices.

• Familiar with B&R Ethercat technology, SAP, ADS and more.

• Performed NPI Plasma group in the design and integration. Panasonic Automotive, Peachtree, GA 8/2017- 12/22/2017 Software/Hardware Verification Engineer:

• Developed Teststand in Labview for integrating Self-driving and Audio automation using Agilent/Keysight U8903B model, Anritsu wireless test set, AVR function generator, NI DIO, DAQ, USB, and etc.

• Tested and debugged both HW test fixture, and UUT. IBM Almaden Research Center, San Jose, CA 8/2015 -6/2017 R&D Engineer in Research Labs:

• Developed C++/Matlab/ Labview code for Plasma/Ion Beam wafer deposition systems and Alpha Beta ion beam systems include CAN/cDAQ, IMAQ, Vxworks, PLC, Bechkhoff Ethercat, Pump/Valve controllers.

• Developed firmware for Robo controller (Vxworks, Vivado, DSP TI studio) and Python for Newport XPS,300 series, Zaber motorized stages and Robotics controller boards and others.

• Supported scientists, PhD, and managed students for complete projects in R&D labs such as Wafer measuring in RF using Signal Gen, Spectrum, Power meter, VNA and others.

• Knowledge in Machine Computing include Deep Learning Algorithm and Neural Net.

• Designed PCB Schematic capture/Layout/Fab using Cadence 16.2. Larson Automation, Inc., San Jose, CA 1/2015-4/2015 Consultant:

• Designed PCB interfaces (Allegro OrCAD CIS 16.2) includes schematics, simulation, layout, test plan, and others related issues include BAE tank vehicle schematics and Charge Point electric vehicle stations.

• Coordinated and consulted works for automations and control includes 802.xx development and troubleshoot design systems.

• Managed team and supported production lines including tests, debugs, and customers. CTS, San Jose, CA 1/2014- 1/2015

Hardware Engineer:

• Managed and supported Aurora, BAE, Google and others for system tests, repairs and maintained 93K, ATE tests in-house with Labview/Python code developing.

• Familiar with RF/Digital Networking (Wifi, Optical, Laser for Aurora, Tropos, etc) using Signal Gen, VNA E5062A, and more.

General Dynamics Adv., Santa Clara, CA 8/11-12/2013 HW FPGA Engineer:

• Created a FPGA model using Veilog/VHDL, Modelsim, Matlab Simulations and Bit map download into FPGA, DSP/WiMAX CPRI UMTS/BB, ADC/DAC, and other FPGA Bus protocols for Satellite Communications Systems.

• Developed algorithm of encrypt/decrypt for security information system.

• Tested and debugged board using NI cDAQ 9178, Signal Gen, VNA E5062A and more.

• Coordinated and developed Labview code with other engineering team. Bitwave Semiconductor, Lowell, MA 8/09 -4/011

Verification Engineer:

• Verified chipset of SDR (software defined radio IC) and coding in C++, UVM/OVM, and Labview automation tests.

• Worked on Xilinx FPGA v.6, DSP/WiMAX CPRI, ADC/DAC, and other FPGA Bus protocols (802.3).

• Tested and debugged board proto and chipset on pilot boards include WiMAX/Wifi/GSM, Signal Gen, VNA E5062A for measurements such as n-QAM/EVM, and more. Xilinx Semiconductor, Campbell, CA 12/06 -5/2009

Staff Engineer and Lab Supervisor/Manager

• Verified Silicon chipset on Wimax, UMTS AXIS BTS and RF board projects on both Baseband/Digital IF/RF sections using OrCAD schematic capture, Xilinx ISE Navigattor EDK/SDK, IFFT/FFT, PSK/n- QAM/EVM, and DSP/WiMAX CPRI, TI CCS C6000 series with fixed floating simulations, C algorithms for Real time DSP, Xilinx FPGA VHDL, Matlab & Simulink, Agilent VSA 896xx series capture tool.

• Created bit stream and implemented ML40x proto boards using 802.3, Ethernet/IO, PCIe, procedures, demo to customers, lab budgets, and parts/instrument orders.

• Familiar with Signal Gen, PXI, VNA and so on.

Anritsu, Morgan Hill, CA 11/00-12/06

HW Development Engineer

• Worked on schematics using Mentor tool and characterized RF design modules such as LNA, PA using MMIC devices, and SONET E1/E3 Networking.

• Performed in developing, designing and supporting floor production on ATE using Visual Basic and Labview/fixture/closure.

Network Test Solutions, Santa Clara, CA 10/91-10/00 Technical Staff Engineer

• Designed custom boards using Cadence 9.2 Schematic Capture/Layout for customers such as Cisco, WirelessLAN, Anritsu and etc.

• Designed PCB test fixture and built-in automations rack for customers.

• Worked on-site customers for developing and implementing code (Perl, Python,C++, Labview/CVI) to those companies and managed our projects and engineering team.

• Supported production lines including tests, debugs, and customers.

• Familiar with RF/Digital Networking using SigGen, Lightpoint, NPR measurement instruments and more.

• Developed Labview code for Digital TxRx and PA modules using VNA E5062A (S-parameter for example), fixture/closure, power supplies and others.

• Coordinated with other team to understand the specification for developing script file. Education

• BSEE Communications Systems and Computer Math at UC San Diego, 1991

• Silicon Technical Institute at San Jose (RF Circuit Design with ADS simulation, Mentor PCB schematic and Layout design), Cadence Capture and Layout.

• Company Training Courses in Labview/CVI, Perl. Visual Studio, Matlab, System Verilog VHDL RTL, Matlab, Xilinx ISE, Python 2.7.

Reference

• Upon your request

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