GAURAV SRIVATSAV RAVISHANKAR

adc9wc@r.postjobfree.com San Jose, CA 562-***-**** www.linkedin.com/in/gauravsrivatsav SUMMARY

Graduate student majoring in MSEE with experience in physical design using Synopsys ICC/ICC2, PrimeTime and StarRC tools at multi-voltage designs at 28nm technology. Good knowledge on STA to verify the design.

EDUCATION

MASTER OF SCIENCE IN ELECTRICAL ENGINEERING

California State University, Long Beach, CA Dec. 2019 Coursework: VLSI Design, CMOS-VLSI, Microelectronics, High-Speed Communication Circuits, Mixed-Signal IC Design, Advanced Microprocessor and embedded control BACHELOR OF ENGINEERING IN ELECTRONICS AND COMMUNICATION ENGINEERING Vidyavardhaka College of Engineering, Mysuru, India Aug. 2017 Coursework: HDL programming, Analog electronics, Digital electronics, Logic Design, Linear Integrated Circuits, Verilog HDL, Microcontroller and Embedded Systems. EXPERIENCE

BLOCK LEVEL IMPLEMENTATION OF 32-BIT RISC CORE PROCESSOR : July 2019- Dec. 2019 o Successfully performed floorplanning, placement, clock tree synthesis and routing. o Design specification: Multivoltage domain(2), 54K standard cells, 40 Macros, 2 Design Corners, Metal layers: 9, supply voltage: 0.9V.

o Target clock frequency: 416 MHz with 6 clocks in design. o Implemented clock ECO to meet timing requirements (setup and hold). o Technology-28nm

o Tools- Synopsys ICC2, PrimeTime and StarRC

PROJECTS

PHYSICAL DESIGN FLOW FROM NETLIST TO GDSII: (ICC, PrimeTime, StarRC) o Floorplanning of the design to with optimum utilization factor and aspect ratio followed by power planning. o Generated congestion report and analyzed Global Route Congestion map to reduce GRC. o Reduced DRC violations and applied ECO fixes to get rid of setup and hold violations at different corners. o Technology-128nm

STATIC TIMING ANALYSIS OF SEQUENTIAL CIRCUIT: (OpenTimer) o Defined the constraints and performed interface analysis. o Analyzed the timing reports and diagnosed the circuit for worst-case delays and identified the worst path delay. o Fixed the setup and hold violation by using the ECO technique in the design. NETLIST TO GDSII IMPLEMENTATION OF 16-BIT MULTIPLIER : (Vesta, Proton) o Synthesized the RTL code using Yosys tool along with pre-layout timing analysis using 'Vesta' tool. o Performed floorplanning, grid power-planning, placement, CTS and Routing in EDA tool 'Proton'. o Observed timing and performed both pre and post-layout STA. o Technology-180nm

16 BIT MULTIPLIER USING WALLACE TREE ALGORITHM ON FPGA KIT: (Xilinx Vivado) o Designed RTL code of 16-bit multiplier based on Wallace tree algorithm with half adder and full adder structure. o Implemented on design on Basys-3 Fpga kit using Verilog on Xilinx Vivado tool using structural description. o Interfaced the push buttons, LED, 7 Segment Display and Switches for inputs and reset using constraint files. AES CRYPTOGRAPHIC ALGORITHM ON FPGA KIT: (Xilinx ISE Design Suite) o Implemented AES on Spartan-7 FPGA using 128 bit key for encryption/decryption in Xilinx ISE Design Suite. o Designed an RTL code using Verilog using both behavioral and structural description. o Analysed internal FPGA signal using Xilinx inbuilt tool ChipScope Pro. TECHNICAL SKILLS

PROGRAMMING LANGUAGES: Pearl, TCL, Verilog, VHDL, SPICE, Assembly language, C, C++ TOOLS: Synopsys Design Compiler, ICC, ICC 2, Star RC, Red Hawk, PrimeTime, Proton, Vesta, Yosys, Cadence Virtuoso, Xilinx ISE design Suite, Microwind, DSCH Schematic editor, Xilinx Vivado, LT Spice, Keil uvision, Hspice. CERTIFICATE COURSES: Physical Design flow, Static Timing Analysis-1, Static Timing Analysis-2, Clock Tree Synthesis-1, Library Characterization, Physical Design webinar using EDA tool ‘proton’, SoC Design of the PicoRV32 RISCV micro-processor.