| Resume alert | Resumes 111 - 120 of 508 |
Electrical Engineering Engineer
Fremont, CA
... Universal Verification Methodology (UVM), Perl Tools: Microsoft Office, MATLAB, Xilinx ISE, Xilinx Vivado, Questa 10.0b, Cadence Virtuoso, PSpice, Synopsys VCS Operating Systems: Windows, Linux ACADEMIC PROJECTS SDRAM Controller Design A SDRAM ... - 2018 Aug 02
... Universal Verification Methodology (UVM), Perl Tools: Microsoft Office, MATLAB, Xilinx ISE, Xilinx Vivado, Questa 10.0b, Cadence Virtuoso, PSpice, Synopsys VCS Operating Systems: Windows, Linux ACADEMIC PROJECTS SDRAM Controller Design A SDRAM ... - 2018 Aug 02
Engineer Design
San Jose, CA
... Cadence palladium Emulation platform for design software and hardware validation for live stimulus and functional coverage Developed and Debugged the various components in Constrained Driven Random Verification Environment including Generating the ... - 2018 Jul 12
... Cadence palladium Emulation platform for design software and hardware validation for live stimulus and functional coverage Developed and Debugged the various components in Constrained Driven Random Verification Environment including Generating the ... - 2018 Jul 12
Engineer Manager
Mountain View, CA
... Has the certificate of the Cadence First and SOC Encounter. Using Laker tool generate the sub block automatically, and its DRC and LVS. Physical design, LVS, DRC and RC extraction and verification. Cadence Tools; Opus, edge, Hspice and Assura, ... - 2018 Jun 27
... Has the certificate of the Cadence First and SOC Encounter. Using Laker tool generate the sub block automatically, and its DRC and LVS. Physical design, LVS, DRC and RC extraction and verification. Cadence Tools; Opus, edge, Hspice and Assura, ... - 2018 Jun 27
CAD/EDA /PDK development/Physical design engineer
Campbell, CA
... SKILL AREAS: TCL, Perl, Shell, Verilog, VHDL, Skill, ocean, Lisp, awk, sed, grep, C, Assembly 88/86/68, Python TOOLS USED: Synopsys, Cadence, Mentor, Agilent/Keysight, Silicon Frontline, Design Sync, Clio Soft, Nassda, Verilog,bda SYSTEMS USED: Sles ... - 2018 Jun 20
... SKILL AREAS: TCL, Perl, Shell, Verilog, VHDL, Skill, ocean, Lisp, awk, sed, grep, C, Assembly 88/86/68, Python TOOLS USED: Synopsys, Cadence, Mentor, Agilent/Keysight, Silicon Frontline, Design Sync, Clio Soft, Nassda, Verilog,bda SYSTEMS USED: Sles ... - 2018 Jun 20
Electrical Engineer Design
San Jose, CA
... Simulation Tools: Cadence OrCAD Capture, Allegro, Xilinx Vivado, SOC Encounter, Matlab. Hardware Kit: Basys3 Artix 7 FPGA Board. Operating systems: Unix/Linux, windows family of operating systems Experience Summary: • Recently graduated electrical ... - 2018 May 24
... Simulation Tools: Cadence OrCAD Capture, Allegro, Xilinx Vivado, SOC Encounter, Matlab. Hardware Kit: Basys3 Artix 7 FPGA Board. Operating systems: Unix/Linux, windows family of operating systems Experience Summary: • Recently graduated electrical ... - 2018 May 24
Design Engineer Electrical Engineering
San Jose, CA
... C, Python, Perl, Verilog, System Verilog, UVM Tools : Xilinx Vivado, ModelSim, Synopsys VCS, Design Vision, NC-Verilog, Cadence Encounter, Design Compiler, GTK Wave, Oscilloscopes Others : Object Oriented Programming, Assertions, Cover groups, ... - 2018 May 20
... C, Python, Perl, Verilog, System Verilog, UVM Tools : Xilinx Vivado, ModelSim, Synopsys VCS, Design Vision, NC-Verilog, Cadence Encounter, Design Compiler, GTK Wave, Oscilloscopes Others : Object Oriented Programming, Assertions, Cover groups, ... - 2018 May 20
Engineer Electrical
San Jose, CA
... Experienced and expert knowledge of most design tools including Cadence Concept schematic capture, Allegro PCB layout tool. Expertise in high speed board design including component selection, schematic capture, PCB layout. Experienced and designed ... - 2018 May 07
... Experienced and expert knowledge of most design tools including Cadence Concept schematic capture, Allegro PCB layout tool. Expertise in high speed board design including component selection, schematic capture, PCB layout. Experienced and designed ... - 2018 May 07
Engineer Software
Santa Clara, CA
... CADENCE DESIGN SYSTEM, San Jose, CA 2010 – 2011 Senior Member of Consulting Staff Software developer in the Spectre team. Built Python based circuit characterization flow tool for TSMC by utilizing direct Spectre API calls, thereby improved ... - 2018 Apr 12
... CADENCE DESIGN SYSTEM, San Jose, CA 2010 – 2011 Senior Member of Consulting Staff Software developer in the Spectre team. Built Python based circuit characterization flow tool for TSMC by utilizing direct Spectre API calls, thereby improved ... - 2018 Apr 12
PCB Layout Designer
San Jose, CA
... Qualcomm – PCB Layout 2011/11 –2016/02 Import nets from Orcad CIS or Cadence Concept HDL to Cadence Allegro, create board outline, parts placement, routing, constraints setup, implement DFA/emn/emp mechanical constraint for high speed multi-layer ... - 2018 Apr 06
... Qualcomm – PCB Layout 2011/11 –2016/02 Import nets from Orcad CIS or Cadence Concept HDL to Cadence Allegro, create board outline, parts placement, routing, constraints setup, implement DFA/emn/emp mechanical constraint for high speed multi-layer ... - 2018 Apr 06
Design Electrical Engineering
Santa Clara, CA
... • Designed and simulated schematic in Cadence with IBM 0.13μm 8HP BiCMOS technology kit as well as layout design and simulation. • Used Monte Carlo Distribution on key parameters (width/length/number of gate figures and etc.) to discover the effects ... - 2018 Mar 29
... • Designed and simulated schematic in Cadence with IBM 0.13μm 8HP BiCMOS technology kit as well as layout design and simulation. • Used Monte Carlo Distribution on key parameters (width/length/number of gate figures and etc.) to discover the effects ... - 2018 Mar 29