Tejaswee Raghav Rayudu

*** *** *******, ***. ****, San Jose, CA, 95126 C: 669-***-**** ac5jbf@r.postjobfree.com Linkedin - www.linkedin.com/in/raghavrayudu/

OBJECTIVE

Seeking a full-time engineering position that provides an opportunity to capitalize my technical skills and abilities in the field of ASIC/SOC Design and Verification

Relevant Coursework

ASIC CMOS Design, Digital Logic Design and Synthesis, System-On-Chip Design and Verification using System Verilog, Advanced Computer Architecture, Digital System Verification using UVM Skills

Programming: C, Python, Perl, Verilog, System Verilog, UVM Tools : Xilinx Vivado, ModelSim, Synopsys VCS, Design Vision, NC-Verilog, Cadence Encounter, Design Compiler, GTK Wave, Oscilloscopes

Others : Object Oriented Programming, Assertions, Cover groups, Constrained Random Testing, Static Timing Analysis, Place and Route, Functional Verification, ASIC Synthesis, Cache Coherency, Coverage Collection, Test Bench Architecture, Pipelines, UNIX, Shell Scripting Protocols : APB, AHB, I2C, PCI-E, SPI

EDUCATION

M.S. in Electrical Engineering Jan 2016 – Dec 2017 San Jose State University, San Jose, CA GPA: 3.6

B. Tech. in Electrical and Electronics Engineering 2011- 2015 Jawaharlal Nehru Technological University, Kakinada, India GPA: 3.8 PROFESSIONAL EXPERIENCE

Jr. ASIC Design Engineer, Scalable Systems Research Labs, USA Feb 2018 – Present

• Working in a team to develop a Multi-level Cache Coherent Protocol for a Shared Multi-Processor System SUMMER INTERN, National Thermal Power Corporation, Visakhapatnam, India June 2014 – July 2014 STUDENT ASSISTANT, San Jose State University, USA March 2017 – Dec 2017 ACADEMIC PROJECTS

Master’s Project: Adaptive Testing Mechanism Based on UVM to Reduce Test Case Redundancy, SJSU

• Verification of a NIOS – II Processor in a UVM Environment and analyzing Line Coverage with Unified Report Generator (URG) Tool in Synopsys

• Python Scripting to parse the HTML Coverage Results and reducing repetition of random stimuli Verification of an Ethernet Switch using System Verilog

• Developed a packet-based verification environment to generate transactions that effectively verify a multi- port Ethernet Switch in System Verilog

• Implementation of the complete verification environment with Driver, Monitor, Checker classes along with Constrained Random Stimuli Generation for the DUT

Controlled Area Network (CAN) Bus Data Transmitter with AHB as a bus master, SJSU

• Designed a CAN transmitter capable of transmitting data, remote, error and overload frames along with bit stuffing and bit timing, completely implemented using System Verilog

• Accomplished synthesis along with the AHB Bus Master version and APB Slave implementation in System Verilog

• Tools: Synopsys VCS

Implementation of Altera NIOS 2 Soft Core Processor, SJSU

• Successfully implemented the instruction set architecture in Verilog that can execute the dot product benchmark

• Datapath design along with hazard detection and forwarding units for handling structural, data, and control hazards

• Tools: Altera ModelSim

Cache Controller Design in Verilog, SJSU

• Implemented the 4 Way Set Associative Cache with FIFO Replacement Policy in Verilog

• Implemented an FSM and a control circuit to compare tags and determine cache hits and cache misses

• Tools: Altera Modelsim

32 port bi-directional Source-routed Network Switch, SJSU

• Developed input port module using state machine in Verilog

• Implemented FIFO, Cyclic Redundancy Checker, along with a simple arbiter Tools: Synopsys VCS

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