JAGANNATH PANDURANGA RAO

415-***-**** ac6ixj@r.postjobfree.com / ac6ixj@r.postjobfree.com https://www.linkedin.com/in/jagannathpandurangarao

** ***** ******, ***** ****, California 94587

PROFILE SUMMARY

Electrical Engineering Graduate Student looking for an internship or full-time opportunities in Digital Design and Verification.

Currently working on UVM based Design Verification at Esencia Technologies using Mentor graphics Questa.

Proficient in Digital Systems, CPU Architecture, Digital Design and Verification (Verilog, SystemVerilog, and UVM).

EDUCATION

The University of Texas at Arlington M.S., Electrical Engineering May 2017

R.N.S.Institute of Technology, Bangalore, India B.E., Electrical and Electronics Engineering June 2014

COURSE WORK

Semiconductor Device Theory (Device Physics), Hardware Descriptive Language, Digital VLSI Design, Analog IC Design, Microprocessor Systems, Silicon IC Fabrication Technology, Digital Signal Processing, Microelectromechanical Systems (MEMS) and Devices.

EXPERIENCE

Esencia Technologies, Design Verification Intern May 2018 – Present

Part of the team verifying Pixel Search Unit(PSU) DUT using UVM in Mentor Graphics Questa

Responsible for writing coverage for the registers and the meta data, and cross coverage for various testcases

Responsible for writing various testcases and scripts to get the seeds of the failing testcases during regression run

SSRLabs, ASIC Hardware Engineer June 2017 – December 2017

Was part of a team designing VlcRAM cache controller and was responsible for Designing finite state machine

Responsible for developing SystemVerilog testbench environment for VlcRAM cache controller in Questa

Developed SV testbench with randomization and assertion based test cases, makefile was written to run the test cases

Maven Silicon Softech Private Limited, Intern May 2014 – May 2015

As part of design and verification team, worked on RTL design, developed SystemVerilog and UVM Testbench environment

Designed Ethernet - PCS sub-component, type 1000BASE-T4 using Verilog HDL and linearly verified the same

SPI IP core verification using UVM - responsible for developing UVM Testbench, generated coverage for verification sign-off

TECHNICAL SKILLS

Languages: C/C++, Verilog HDL, System Verilog, Universal Verification Methodology (UVM), Perl

Tools: Microsoft Office, MATLAB, Xilinx ISE, Xilinx Vivado, Questa 10.0b, Cadence Virtuoso, PSpice, Synopsys VCS

Operating Systems: Windows, Linux

ACADEMIC PROJECTS

SDRAM Controller Design

A SDRAM controller was designed for interfacing multiple MT48LC8M8A2 SDRAMs with 80386DX microprocessor

The controller provides state machine, data masking, data flow, ready logic, row, column, and bank signal generation

FSM was designed using Verilog HDL in Xilinx Vivado and was linearly verified with few basic test-cases

Verification of Dual-Port Ram, 4-bit mod-16 Bi-Directional Counter using SystemVerilog

•Developed the SV Test bench environment with constraint randomization and SV based assertions in Questa

•Formally Verified various test cases, generated code and functional coverage report for verification sign-off

UART (Universal Asynchronous Receiver/Transmitter) protocol Design Verification

Responsible for developing UVM test bench from scratch, developed Coverage Model and Scoreboard for IP

Features verified were Loop Back, Full and Half Duplex Mode, Transmission and Reception with Parity and Frame Error

Verified the DUT using assertions and met the functional coverage requirements using Mentor Graphics Questa

AXI 4 Verification IP Development

Responsible for developing UVM test bench from scratch, developed Coverage Model and Scoreboard for IP

Features supported are write transaction, read transaction and out of order transaction

Wrote testcases for sanity checking and created makefile for execution in Mentor graphics Questasim

The design is re-configurable and can be used as plug and play for various SOCs

Design of cache controller for a 32-bit processor

•The microprocessor is a general purpose in design and performs number of functions, it is also desired to speed up certain signal processing functions, such as a Fast Fourier Transform (FFT) routine

•The best architecture for a cache controller was designed to interfaces a 32- bit microprocessor with a 32-bit data bus which includes optimized associative set size, the number of lines, burst length, write and replacement strategy

Fabricated MOS Capacitors in clean-room environment

Additional Skills: Experience in Functional verification, Assertions, Functional Coverage, random-Constraint Testbench verification, Regression, CPU Architecture, Static Timing Analysis(STA), CMOS Circuits, FPGA Architecture, Cache memory, ASIC design flow

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