Engineer Electrical

TRI NGO

**** ******** **. ********, **. *****

Work: 408-***-****

Email: ac5dp5@r.postjobfree.com

OBJECTIVE:

Looking for a hardware engineering position in board design/board bring up.

SUMMARY:

Strong back ground hardware board design include: SOC (Broadcom, DSPG,TI), memory (DRR2, DRR3, DDR4, LPDDR3), network interface (10/100/1000Mbs), video, LCD, Audio speaker interface, Bluetooth, Wi-Fi, USB.

Strong experienced hardware boards bring up, debug, validation hardware features.

Experienced and expert knowledge of most design tools including Cadence Concept schematic capture, Allegro PCB layout tool.

Expertise in high speed board design including component selection, schematic capture, PCB layout.

Experienced and designed the power over Ethernet (Maxim, Linear and TI POE devices), DC-DC power convert, LDO.

Experienced EMC design, debug, fix and run the EMC compliance FCC US/CAN, EU, and worldwide (WW) in compliance lab.

Communication skill, inter-active to work with layout engineer, mechanical, manufacturing, software, product market

Strong skill debug tools such as Oscilloscopes, Logic Analyzers, Vision Ice/CodeTap, Fire.

EXPERIENCE:

Cisco Systems, Inc., San Jose, CA. 05/2000 to 04/2018

Hardware Engineer, IP phone Group.

Responsible and designed of multiple Cisco IP phones that covered those features interface: SOC interface (Broadcom, DSPG, TI)), memories (Flash, DDR2, DRR3, DDR4, LPDDR3), network interface (10/100/1000MBS), Video, Camera, LCD, Audio speaker interface, BT/Wi-Fi interface, peripheral interface (RS232, RJ45, USB2, USB3, HDMI).

Responsible to work with vendors, select and qualify components on board design and cost saving

Using Cadence Concept schematic captured, generated netlist, write the guide line for layout

Experience and designed the power over Ethernet (Maxim, Linear and TI POE devices), DC-DC power convert, LDO, power signal integrity concepts such as impedance, different routing, insertion loss, board stack up.

Successful delivered multi Cisco IP phones to the industry:

-CP-8832 conference phone with features: 10/100MBS, BT/Wi-Fi, power over Ethernet(POE), single USB3 cable provided power and Ethernet to share one cable connected to phone.

-DX70, 14 inches LCD touch screen Desktop Video phone, 10/100/100MBS, BT/Wi-Fi, POE, HDMI input.

-DX80, 23 inches LCD touch screen Desktop Video phone. 10/10/100MBS, BT/Wi-Fi, POE, HDMI input.

-CP-8851, CP-9951, 5-inch color display LCD, Video phone, 10/10/100MBS, BT/Wi-Fi, POE, HDMI input.

-CP-7942/62 with POE, 10/100MBS.

-CP-7940/60 early Cisco IP phone, 10/100MBS.

Worked closely with mechanical team regarding cable define, thermal analysis, heat-sink, MDVT requirement for phone board.

Worked with firmware Engineer to development boot-code and for board bring-up and debug hardware features.

Worked closely with NPIE on manufacturing BOM release, Fab review, DFM and phone built.

Worked with CAD engineer on PCB board layout, prototype builds and manufacturing issues.

Experienced EMC compliance design, debugged and fixed EMC issue. Working side by side with compliance test engineer set up and run the test.

In depth knowledge and expertise FCC US/CAN, EU CISP32/EN55032, Worldwide (WW) standard requirement.

Cisco Systems, Inc., San Jose CA.

Hardware Engineer, Optical Networking Group (ONG)

Designed the Timing control card (TCCI) that provided the key control functions and timing for the ONS15454E platform one of Cisco’s new technologies. TCCI card consist of a dual MPC860 32 bits, Flash, SDRAM, 10/100MBS Ethernet, RS-232 craft port, Stratum 3 clock, In/Out BITS providing E1, 2 MHz square wave.

Performed characterizing, testing and debugging of Cross connection card (XCVXL) on a critical product release which including configuration of network, system set up and provisioning circuits to run traffic test, and to run Pre-EDVT tests at the chamber.

Designed a fan control card for ONS15310 platform to control fan speed which is essential to keep platform cool, and to determine fan and fuse failure.

Designed an alarm card which provides alarm input/output, Order-wire and User data channel.

Campio Communications, Inc., Milpitas, CA. 11/198 to 5/2000

Hardware Engineer

Responsible for design 12-Port LAN interface, including Fast-Ethernet 10/100MBS, Gigabit-Ethernet, PPC processor.

Experienced on design Hot Swap interface circuitry, serial ports, console port,

Microprocessors, high speed SRAM, DRAM, complex PLD, high speed Bus, and clock termination.

Write design specification, debug and release to manufacturing.

Designed T1/E1/CES module interfaces with UTOPIA bus, including local CPU, SRAM memory, Altera CPLD/FPGA

Designed and implemented DS3/E3 I/O module which provides to WAN access.

Designed and implemented OC-3 module

EDUCATION

B.S. in Electrical Engineering, San Jose State University.

Continue an education in Cisco and skill learning program.

REFERENCE

Available upon request.

Contact this candidate