Man Kam Johannes Hsieh

Santa Clara, CA

https://www.linkedin.com/in/johannes-hsieh/

ac4333@r.postjobfree.com 408-***-****

Result-Oriented Software Developer

Lead delivery of Electronic Design Automation (EDA) software solutions to circuit designers, improving productivity, accuracy, and time to market

Key strengths in conceptualizing, scoping, scheduling, software implementing, training team members, and problem resolution. Known as a hands-on troubleshooter with solid background in EDA software developments, Perl, tcl/tk, C++, Python, R, numerical analysis, and some machine learning applications.

Employment

ORACLE, Santa Clara, CA 2011 – 2017

Principal CAD Software Engineer 2016 – 2017

Technical lead in statistical circuit performance / yield and optimization tools (developed with Perl, C++, R, Python)

Built and successfully deployed statistical circuit performance / yield tool.

Reduced production costs by significantly reducing design margins needed. Utilized statistical methods in deriving effective corners which decreased margin provided by wafer foundry.

Utilized Design of Experiment (DoE) and statistical method, generating efficient seeds for global and local variations, which led to more accurate sampling and reduced number of simulations.

Achieved target circuit yields by utilizing novel iteration method that improved performance, resulting in improved run time and enhanced designer productivities.

Utilized various parallel run modes in optimizing run time in different compute resource situations. Greatly improved flexibility in utilizing computing resources and therefore improved productivity of customers (circuit designers).

Met all development milestones and beat delivery schedule.

Provided training and guidance to new team members regarding methodologies and code base, leading to rapid ramp up in team productivity.

Senior CAD Software Engineer 2011 – 2016

Lead developer in circuit optimization and statistical corner generation tools (developed with Perl, C++, R, Python)

Built tools to optimize circuit measurements such as timing, power, and area, reduced costs while enhancing circuit performance as well as improved designer productivities.

Generated efficient simulation parameter seed utilizing statistical methods and resolve linked and related circuit parameters, which leaded to more accurate sampling and therefore results.

Utilized unguided machine learning method to iteratively improve solutions and provide designer with alternative optimization choices. This novel technique improved optimization by 8 to 15% over the usual method, together with the choice in optimized solutions, can lead to significant cost savings and circuit performance.

Employed various optimization methods in achieving competing circuit measurement targets, which leaded to performance gain while reduce power and / or area consumed.

Improved and maintained internal statistical circuit corner generation tool.

CADENCE DESIGN SYSTEM, San Jose, CA 2010 – 2011

Senior Member of Consulting Staff

Software developer in the Spectre team.

Built Python based circuit characterization flow tool for TSMC by utilizing direct Spectre API calls, thereby improved efficiency and performance.

Improved performance of Spectre / APS (C++) by improving part of the BBD parallel matrix solver – refactored matrix components to optimize core utilization.

WATT MINDER, Sunnyvale, CA 2009 – 2010

A pre-venture Solar Power Plant Diagnostics and Production Assurance Startup Company.

Software Systems Architect

Developed data mining software for solar power failure monitoring.

Designed software systems to monitor and diagnose solar power plants.

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WATT MINDER (Continued)

Built models to categorize solar panel performance matrix.

Studied various solar power plant data with data mining and neural network.

XOOMSYS, INC., Cupertino, CA 2006 – 2009

Senior Software Developer for Advanced Technology

Oversaw simulation convergence strategy and implementation (C

Achieved internal simulator performance speed-up (by 10X in some circuits).

Improved internal simulator spice model accuracy and characterization.

Improved circuit partition methodology (such as MinCut and other graphic methods) which leaded to performance improvements.

Provided solutions to evaluate circuit accuracies, performance, and convergence of various circuit simulation acceleration schemes.

Developed circuit error checks and circuit characteristics checks after circuit data import.

Developed perl scripts to perform various circuit partitioning checks in geometry and measurements, resulting in finding many hidden bugs and prevent shipping buggy software to customers.

INFINISIM, INC., Alviso, CA 2005 – 2006

Senior Staff Engineer

Managed improving of SPICE simulator performance (C

Developed interconnect R(L)C reduction solutions – implemented AWE, Exponentially Decaying Polynomials, Recursive Convolution, State-Space Realization integrated PACT methodology, coupling capacitor process in DSPF file. Resulted in run time improvements.

Derived and implemented several sparse matrix linear solvers, including Cholesky, non-symmetric, BBD, minimum degree reduction, and GMRES. Improved solver performance and enabled the utilizing of distributed / multi-threaded computing mode for matrix solutions.

Developed scripts to translate customer circuit files into DSPF file for simulation.

PDF SOLUTIONS, INC., San Jose, CA 2000 – 2005

Consulting Software Engineer

Main developer for internal yield impact simulation and analysis tool YRS. One of the 1st developers of PDF Solutions’ industrial leading YRS (Yield Ramp Simulator) software, which predicts chip yield based on design, attributes. Had been continuously contributing / developing the yield predicting tool since 2000. Extensively used by yield enhancement engineers and customers as well as engagement managers. Clearly reported yield impacts by all production processes and pinpoint significant yield impact sources. This tool helped company to negotiate contracts while provide clarity for engineers to the problem areas.

Developed the following:

oYield models based on layout design attributes for YRS. Provided solutions for design for manufacturability issues.

oCMP (Chemical Mechanical Polishing) simulator based on physical model. More accurate in pinpointing defect areas on chips due to CMP non-uniformity.

oFeatures and methodologies of layout extraction tool, lead to increased coverage in yield impact sources. Collaborated with in-house staff.

oGUI with tcl/tk for yield calculation, combining tcl/tk scripts, layout extraction tools, c dlls and Excel Macros / VBA in 1 GUI environment. Reduce yield calculation / extraction complexity and thereby improve productivity by more than 4 to 100 times.

oLinear and non-linear analytic tools with C / C++ as dlls for Excel VBA to analyze defect parameters that impact yield. Developed various software tools and utilities to add functionalities and usability of the YRS Excel tool.

Contributed in significant increase in “Gain Share” sells revenue.

Wrote install shell scripts, software packing, and develop software-licensing (FLEXLM) methodologies to distribute software.

Performed advance extractions for consulting groups.

Specified test and use cases and performed software testing using / writing winRunner scripts.

Suggested methods to increase yields, based on extraction results and layout attributes.

Trained customers in using software tools.

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Education

PhD, Electrical and Computer Engineering, University of Wisconsin – Madison, Madison, WI

Thesis: Full Wave Simulation of Electron Cyclotron and Helicon Plasma Processing Systems

MS, Electrical and Computer Engineering, University of Wisconsin – Madison, Madison, WI

BS, Electrical Engineering, Boston University, Boston, MA

Project and Program Management Certificate with Honors, University of California, Santa Cruz Extension

E-Business Certificate: University of California, Santa Cruz Extension

Certificate in Professional Effectiveness Program

(Communicating, Team Building, and Problem Solving in the Workplace): NOVA

Additional Experience

INTEL CORPORATION, Santa Clara, CA

Senior CAD Engineer, Technology CAD Department

DIGITAL SEMICONDUCTOR / INTEL CORPORATION, Hudson, MA

Senior Manufacturing Engineer, TCAD

RESEARCH CENTER FOR PLASMA AIDED MANUFACTURING and Center for Plasma Theory and Computation

University of Wisconsin – Madison, Madison, WI

Research Assistant

N.V. NEDERLANDSE GASUNIE, Groningen, The Netherlands

Industrial Intern

Languages and Citizen Status

English and Chinese (native fluency in both Mandarin and Cantonese)

Citizen of United States

Computer Skills

Perl, Python, R, C / C++, tcl/tk, VB/VBA (Excel and Access), Java, Installshield Script, Fortran 77, HTML, Pascal, UNIX, shell script, VMS

Publications

R.T.S. Chen, R.A. Breun, S. Bross, N. Hershkowitz, M.-K. Hsieh, and J. Jacobs, “Experimental studies of multimode helicon plasma waves”, Plasma Sources Sci. Technol. pp.337 – 344, 4, 1995

F.F. Chen, M.J. Hsieh, and M. Light, “Helicon waves in a nonuniform plasma”, Plasma Sources Sci. Technol. 3, 49, 1994

D. Diebold, N. Hershkowitz, J. Dekock, T. Intrator, S.-G. Lee, M.-K. Hsieh, “Space Charge Enhanced, Plasma Gradient Induced Error In Satellite Electric Field Measurements”, Journal of Geophysical Research, pp.449 – 458, Vol.99, No. A1, Jan. 1994

F.F. Chen and M.J. Hsieh, “Collisionless ExB Instability in Regions of Strong Electric Shear”, Proc. Int’l Workshop on Magnetic Turbulence and Transport, Cargese, France, pp.56 – 69, 1992

D. Diebold, C.E. Forest, N. Hershkowitz, M.-K. Hsieh, T. Intrator, D. Kaufman, G.-H. Kim, S.-G. Lee, and J. Menard, “Double-Layer-Relvant Laboratory Results”, IEEE Transactions on Plasma Science, pp601-606, Vol.20, No.6, Dec. 1992

D. Diebold, M.-K. Hsieh, N. Hershkowitz, J. DeKock, and T. Intrator, “Satellite Probe Electric Field Measurements And The Effects Of Space Charge”, p.87, Conference Record-Abstracts, 1990 IEEE International Conference on Plasma Science, May 1990

D. Diebold, M.-K. Hsieh, N. Hershkowitz, J. DeKock, and T. Intrator, “Space Charge Effects on Satellite Electric Field Measurements”, Tran. Am. Geophys. Union, p1288, Vol.70, San Francisco, CA, Dec. 1989

D.T. Anderson, F.S.B. Anderson, M.J. Hsieh, P.G. Matthews, and J.L. Shohet, “Diverted Plasma Flows in the Proto-Cleo Stellarator”, p1930, Series II, Vol.34, No.9, Bulletin of the American Physical Society, Anaheim, CA, Oct. 1989

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