Engineer Manager

Jianmin Zhang

**** ****** ****** #*

Mountain View, California 94041

Tel 408-***-**** (Home)

408-***-**** (Cell)

Professional Summary:

Experience in Full chip backend design integration, and management.

Chip level edit, floor plaining and tape out.

Analog and digital customer layout.

I/O PAD, memory full custom layout design including floor planning.

Has the certificate of the Cadence First and SOC Encounter.

Using Laker tool generate the sub block automatically, and its DRC and LVS.

Physical design, LVS, DRC and RC extraction and verification.

Cadence Tools; Opus, edge, Hspice and Assura, Dracula, etc.

Cache related circuit design.

Familiarity with CAD environment setup, and, back end team setup in china.

Familiarity tools, such as Cadence tools: Virtuso, Dracula, Hspice, SOC encounter

Synopsys: Pathmill, Arcadia, and timill (EPIC tools)

Metor Graphics: Calibre, Excabre.

Education:

M.S. Electrical Engineering, Louisiana Tech University (LTU), Ruston, LA Jul 93

M.S. Electrical Engineering, Shanghai Jiao Tong University, Shanghai, China, May 89

Professional Experience:

Kiloway Technologies Corp

Apr 09 - Jul 17

Senior Product Manager

Silicon blue Technologies Corp

Jul 06 - Jan 09

Senior Design Manager

Design and Managing backend effort of the company’s test chips and products from 0.065um, 0.09umprocessing technologies.

Backend design environment set up and management

Lead projects from specification development to final product.

Kilopass technology Inc.

Jan 02 - Jul 06

Senior Layout Design Manager

Setup and trained layout team for the customer layout to chip tape out in china.

Design and Managing backend effort of the company’s test chips and products from 0.35um, 0.18um to 0.13um, and 0.09um processing technologies.

Multiple foundries designs and tape outs.

Backend design environment set up and management.

Trident Microsystems and Light Speed.

Oct 01 - Jan 02

Backend design

IO floor planning, and its customer layout

Customer block and cell layout, digital and analog

Cadence Design Systems. Inc.

May 01 - Sep 01

Leader Services Application Engineer

Assura, Dracula, LVS, DRC verification tools support

Market Research Application Engineer

NEC Electronics Inc.

Oct 97 - Apr 01

Staff Design Engineer

Circuit Design:

I/O design which including simulation, power bounce, esd consideration, etc.

Dcache and Icache simulation by HSPICE and time Mill.

Timing Analyze by Path Mill to check the slake for the timing delay.

Whole chip verification by Dracula LVS and ruler file modification.

Whole chip static timing analysis, which includes the RC loaded by EPIC tool (SYNOPSYS tools)

Physical design:

I/O Pad floor planning and layout.

Full layer chip tape out.

Trident Microsystems Inc.

Apr 94 - Oct 97

Senior ASIC Engineer

Hspice simulation on I/O buffers, full chip floor planning, partition, and aspect ratio assignment.

Writing Drcula and modifying LVS and DRC tech file, I/O buffers layout and IBIS model setup.

IO customer layout and IBIS model create to the customer.

Performing advance graphic and multimedia chip design related tasks which including schematic entry and net listing, layout planning and detailed custom layout, block and top level editing, full chipDracula LVS, LPE, DRC verification and final chip tape-out.

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