Mohammed Hossain

Cupertino, CA ***** 408-***-****, 408-***-****

ac5ya6@r.postjobfree.com www.linkedin.com/in/mohammed-hossain-6584294

EXPERT IN PHYSICAL DESIGN/IMPLEMENTATION,ASIC

Develop Efficient Tools/Scripts to Enhance Productivity and Time to Market

Individual utilizing exceptional technical skills and knowledge to create methods for Physical design engineers. Self-directed, collaborative, and approachable with ability to communicate complex ideas easily and clearly to meet objectives.

SKILL AREAS: TCL, Perl, Shell, Verilog, VHDL, Skill, ocean, Lisp, awk, sed, grep, C, Assembly 88/86/68, Python

TOOLS USED: Synopsys, Cadence, Mentor, Agilent/Keysight, Silicon Frontline, Design Sync, Clio Soft, Nassda, Verilog,bda

SYSTEMS USED: Sles Linux, Red Hat Linux, UNIX operating system, Citrix/MFU, NoMachine, Vmware, Windows 10

EMPLOYMENT HISTORY

Qualcomm, Santa Clara, CA 2013 – Present

SENIOR STAFF ENGINEER

Implemented Netlist to GDS of digital designs. Integration and support of vendors and internal EDA applications and flows in analog/RF circuit design, physical design, parasitic extraction, physical verifications, version control tools, and Tapeout support and review. Create Pcell to generate schematic-driven layout in Cadence Virtuoso-XL and EDA scripts in Cadence skill, ROD, and Perl. Develop DRC, LVS, and parasitic extraction runset files in Calibre and Assura.

Implemented Netlist to GDS of digital designs. Completed floor planning and partitioning, synthesis, formal verification, place and route, clock tree synthesis, signal integrity analysis and timing closure with different process nodes of 14nm, 16nm and 28nm .

Developed and implemented plans to synthesize, implemented including Design-For-Test (DFT) and close timing on complex digital integrated circuits at the block level (100K to 1M+ gates) which are coded in VHDL/Verilog .

Designed, implemented and maintained synthesis, DFT and Static Timing Analysis scripts using best-in-class methodologies Extensive experience in static timing analysis, power and noise analysis and back-end verification across multiple projects .

Analyzed log and report files to ensure the tools are getting the required results and make adjustments to the scripts to get the required results within the scheduled milestones . with backend design EDA tools Synopsys or Cadence .

Experienced in Design-For-Test tools & methodologies (Scan chains, ATPG, BIST, Fault models, Fault Coverage and generation). Experienced with Verilog/VHDL and Digital Design Principles .

Worked with various design groups across different disciplines (Logic, Circuits, DFT & Layout) to meet timing closure, area, power, and performance requirements .

Successfully track records of taping out complex SOC in 16nm and beyond . Working knowledge of deep sub-micron routing issues as they relate to power and timing .

Strong scripting skills in Perl, TCL and Shell, particularly in synthesis & timing analysis . Communicated regularly with the project teams world-wide to resolve issues and to ensure meeting targeted goals and schedule .

Ported / migrated design from one technology node to another by creating database (layout and schematic) translation/migration tools using Cadence skill.

Provided quality PDKS in timely manner and improved design efficiency without silicon respin by instituting robust test / validation methodologies for custom / foundry PDKs and installing, developing, validating, updating, and maintaining all RF / analog custom and foundry PDKs, standard cell and I/O libraries with different process nodes of 14lpprf, 14lpcrf, 16ff, 28nm, 65nm, 150nm and 180nm.

Developed new tools and methods to further automate commercial tools by creating configuration file, GUI, and essential functions for R3D/RMAP, schematic design capture, ADE/ADEXL simulation (Spectre, AMS, bda, Golden Gate), layout tools such as skillCAD, VXL schematic to layout device placement, Calibre/Assura DRC, LVS, xRC, and LPE back annotation.

Constructed high-performance custom devices, inserting into custom libraries and enabling necessary views for simulation, layout, physical verification, and parasitic extraction. Saved money on Assura licenses by generating CAD automation scripts for Metal/Poly fill, Metal slot, XOR, and ANTENNA tool.

Microsemi Corp., San Jose, CA 2012 - 2013

SENIOR STAFF CAD ENGINEER

Provided extensive expert support to design team for all CAD, PDK, and design flow issues. Supported and managed design database management tool Cliosoft and maintenance of Linux infrastructure to provide world-class simulation times. Installed, updated, and supported EDA tools for schematic capture, simulation, physical design, DRC/LVS, ERC, extraction, analog / mixed-mode simulation, and verification. Developed quality design methodologies and flows.

Delivered quality devices, developing custom PDK for internal and external foundries for multiple process nodes and creating custom devices for insertion into custom libraries with necessary views for simulation, layout, physical verification, and parasitic extraction.

Provided efficient environment for design team and improved time to market by instituting world-class test / validation methodologies for custom / foundry PDKS, creating Pcells to generate schematic-driven layout in Cadence Virtuoso-XL, and developing new EDA tools and scripts (SKILL, OCEAN, PERL, TCL/TK and Unix Shell) to integrate and extend commercial CAD tools.

Created custom DRC, LVS, extraction runset files for physical verification and parasitic extraction (Calibre and Assura) and provided excellent tapeout support by preparing eTapeout paperwork to final GDS file ftp transfer, JobView, Mask, and lot tracking.

Facilitated improvement in product design through representation and interface as primary contact with foundry XFAB, Global Foundry, TSMC, IBM, Tower Jazz, Magnachip, EDA vendors, and IP vendors for all foundry-related design issues related to 0.18um/65nm RF/mixed signal and 0.18um/65nm logic processes.

Supported all RF / analog / ASIC EDA tools (Cadence IC615 and IC514 Virtuoso/Composer/ADE-L/ADE-XL/Spectre/Assura/AMS Designer/NC-Verilog/Conformal/RTL Compiler/SOC Fist Encounter, Mentor Simvision, Questa, Calibre, Synopsys Primetime, Logicvision, and Cliosoft on RH 6.0 and ENT 5.0 32 and 64-bit Linux platforms displaying with Putty and VNC.

Amalfi Semiconductor, Los Gatos, CA 2005 - 2012

CAD MANAGER

Led team of CAD/EDA engineers to support design and enhancement of state-of-the-art analog and mixed-signal designs. Developed innovative, analog mixed-signal design methodologies for advanced technology nodes to enable efficient design and development of products. Created and supported parasitic extraction and re-simulation flows and differentiated CAD solutions for high-frequency operations, circuit robustness, and reliability. Established design for manufacturability guidelines for supported process nodes and created physical verification flows. Collaborated with EDA vendors and worked with design and layout community to facilitate implementation and support of flows.

Developed world-class design methodologies and flows for wireless chip design, introducing new CAD/EDA tools and automation scripts for front-end and back-end and integrating and extending commercial CAD tools.

Built critical tools such as metal / poly fill generation, metal slot generation, XOR, and ANTENNA and also generated script and methodology to run corner simulation, sweeping all corners and overlaying results on same waveform viewer window.

Managed all RF / analog / ASIC EDA software and budget mainly Cadence IC5141 Virtuoso/Composer/ADE/Spectre/Assura/AMS Designer/NC-Verilog/Conformal/RTL Compiler/SOC Fist Encounter, Agilent ADS & RFDE, Synopsys Primetime and Logicvision on RH 8.0 and ENT 4.0 32 and 64-bit Linux Platforms displaying with Cygwin, VNC, and Hummingbird Exceed. Saved company money by negotiating with EDA vendors and using licenses efficiently.

Earned reputation as ‘go-to’ person for resolving complex issues by providing extensive support and training to designers on tools and reviewed and provided Tapeout Support from preparing foundry eTapeout paperwork to final GDS file ftp transfer, JobView, Mask, and lot tracking.

Interfaced as primary contact with vendors for all foundry-related design issues related to TSMC/IBM (CSOI7RF 0.18um/90nm RF/mixed signal and 0.13um/65nm logic processes by providing software installation, licensing, configuration, updates, customization, and debugging.

Managed design database, ensuring product design was executed with latest technology to guarantee superior performance.

ADDITIONAL PROFESSIONAL EXPERIENCE

Volterra Semiconductors, Fremont, CA

SENIOR STAFF CAD ENGINEER,

Philips Semiconductors, Sunnyvale, CA

SENIOR STAFF CAD ENGINEER

C-Cube Microsystems Inc., Milpitas, CA

STAFF CAD ENGINEER

Analog Devices, Inc., Santa Clara, CA

SENIOR CAD ENGINEER

EDUCATION

Master of Science (MS), Electrical Engineering, Utah State University, Logan, UT

Bachelor of Science (BS), Electrical Engineering, Utah State University, Logan, UT

Associate of Science (AS), Engineering, Snow College, Ephraim, UT

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