Electrical Engineer Design

Educational Qualification:

Masters in Electrical engineering

(WNEU): 3.86 GPA (December,

2017)

Bachelors of Engineering

(BNMIT): 3.1 GPA

Skills/Tools:

Languages: Verilog, Python.

Simulation Tools: Cadence

OrCAD Capture, Allegro, Xilinx

Vivado, SOC Encounter, Matlab.

Hardware Kit: Basys3 Artix 7

FPGA Board.

Operating systems: Unix/Linux,

windows family of operating

systems

Experience Summary:

• Recently graduated electrical engineer from Western New England University.

• Hands-on project experience using Xilinx Artix 7 Basys 3 kit and Vivado design suite.

• Hands-on project experience using Orcad schematic capture and Allegro layout tool.

• Knowledge of RTL design, clock tree synthesis, circuit design, PCB design using CAD tools, signal integrity, signal processing, EMC/EMI, silicon board bring-up.

• Lab experience and familiarity with basic lab equipment, including digital oscilloscopes, analog and digital voltmeters, ammeters, spectral analyzers and VNA measurements.

• Knowledge of PLLs, ADCs, DACs, Sigma Delta Modulators, Op-Amps, wireless comm.

•Knowledge of high-speed signal interface standards such as USB2/3, DDR2/3, SATA, DP, HDMI.

KARTHIK MAHESH RAO

****.*******@*****.***

+1-669-***-***

https://www.linkedin.com/in/karthikmaheshrao

Objective: Seeking an exciting Hardware Design Engineer position (RTL/FPGA/PCB/Silicon validation) in a reputed organization.

Project Experience:

• Clock Tree Synthesis:

I ran CTS under different scenarios to understand the clock tree synthesis behavior with different variables being set using buffer list and inverter list to obtain minimum skew.

• FPGA based design and Implementation of Stopwatch and digital watch: Verilog codes were written to design digital watch, stopwatch. Vivado design suite is used for synthesizing the code and the output is observed on Basys3 Artix 7 FPGA kit.

• Schematic and layout design using Orcad Capture and Allegro: A PCB design was implemented for integrated Buck Regulator.

• Measuring Transmitter performance for WCDMA using ACLR: Investigate the transmitter performance for WCDMA using the concept of ACLR. The performance was analyzed using the Matlab software.

• Serial Peripheral Interface:

Devices communicate in master/slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual slave select (chip select) lines. A Verilog code for was written to demonstrate the SPI transfer.

Extra-Curricular:

• National Medalist in Swimming.

• Part time teacher for physically and mentally challenged kids.

• Organizer for Blood donation camps.

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