| Distance: | Resume alert | Resumes 11 - 20 of 6502 |
Embedded systems engineer
Lee, MA
... of Science in Computer Engineering: GPA 3.11 Technical Skills Python programming, MATLAB, Microsoft Word, Excel, PowerPoint, C++, GDB, g++, Risc-V Assembly, Verilog, Linux systems, Quartus Prime, VLSI, Bash, Virtuoso, Hspice, LTSpice, Cadence. ... - Jun 23
... of Science in Computer Engineering: GPA 3.11 Technical Skills Python programming, MATLAB, Microsoft Word, Excel, PowerPoint, C++, GDB, g++, Risc-V Assembly, Verilog, Linux systems, Quartus Prime, VLSI, Bash, Virtuoso, Hspice, LTSpice, Cadence. ... - Jun 23
Power Electronics Circuit Design
Tempe, AZ, 85281
... Engineering Mumbai, Maharashtra, India • Coursework: Digital Systems and Design, Circuit Theory and Networks, Linear Integrated Circuits, Signals and Systems, Digital VLSI, Mixed-Signal VLSI, Microwave, Electromagnetics and Antenna, Microwave. ... - Jun 20
... Engineering Mumbai, Maharashtra, India • Coursework: Digital Systems and Design, Circuit Theory and Networks, Linear Integrated Circuits, Signals and Systems, Digital VLSI, Mixed-Signal VLSI, Microwave, Electromagnetics and Antenna, Microwave. ... - Jun 20
Senior Product Manager
San Diego, CA
... in Electrical Engineering, Illinois Institute of Technology (2003-2005) Thesis on VLSI Clock Distribution Networks in Silicon Chips, contributing to the field with papers published in multiple academic journals. PROFESSIONAL AWARDS Emerging Leaders ... - Jun 19
... in Electrical Engineering, Illinois Institute of Technology (2003-2005) Thesis on VLSI Clock Distribution Networks in Silicon Chips, contributing to the field with papers published in multiple academic journals. PROFESSIONAL AWARDS Emerging Leaders ... - Jun 19
Design Engineer Security Clearance
Madison, AL
... LOCKHEED MARTIN AT NASA / GSFC, Greenbelt, MD 1993 – 2001 Senior R&D Engineer Conducted research and development of new technologies, architectural and logic design, simulation, test, and characterization of very-large-scale integrated (VLSI) ... - Jun 15
... LOCKHEED MARTIN AT NASA / GSFC, Greenbelt, MD 1993 – 2001 Senior R&D Engineer Conducted research and development of new technologies, architectural and logic design, simulation, test, and characterization of very-large-scale integrated (VLSI) ... - Jun 15
Operations Center Network
Orlando, FL
... Accomplished functional design for VLSI integrated circuits. Performed stress analysis, Worst-case timing analysis. Security Clearance level – Secret Resume’ -- Herbert A. Teague SPECIAL SKILLS/EXPERTISE NOC Tech ATM Network Surveillance and Repair ... - Jun 13
... Accomplished functional design for VLSI integrated circuits. Performed stress analysis, Worst-case timing analysis. Security Clearance level – Secret Resume’ -- Herbert A. Teague SPECIAL SKILLS/EXPERTISE NOC Tech ATM Network Surveillance and Repair ... - Jun 13
Design Engineer Hardware
Dublin, CA
Harshith Reddy Surakanti Dublin, CA ********.*********@*****.*** +1-317-***-**** EDUCATION Purdue University Indianapolis Indianapolis, IN MS in Electrical and Computer Engineering (VLSI) Fall’2024 (GPA: 3.4) Coursework: SoC Design, MOS VLSI Design, ... - Jun 11
Harshith Reddy Surakanti Dublin, CA ********.*********@*****.*** +1-317-***-**** EDUCATION Purdue University Indianapolis Indianapolis, IN MS in Electrical and Computer Engineering (VLSI) Fall’2024 (GPA: 3.4) Coursework: SoC Design, MOS VLSI Design, ... - Jun 11
Systems Engineer Computer Engineering
San Diego, CA
Aghared Shaba San Diego, CA *********@*****.*** LinkedIn: Aghared Shaba GitHub: aghared Summary Recent Computer Engineering graduate knowledgeable in digital systems design, embedded systems, and VLSI. Familiar with Verilog, C, C++, Python, and Java ... - Jun 11
Aghared Shaba San Diego, CA *********@*****.*** LinkedIn: Aghared Shaba GitHub: aghared Summary Recent Computer Engineering graduate knowledgeable in digital systems design, embedded systems, and VLSI. Familiar with Verilog, C, C++, Python, and Java ... - Jun 11
Fpga Engineer Hands-On
Sacramento, CA
... VLSI Design Intern, 3D Ed Tech PVT. LTD. Jan 2022 – May 2022 • Applied Verilog HDL, Linux, and C programming for hardware design. • Acquired hands-on expertise in VLSI design methodology and FPGA optimization. • Specialized in FPGA design, focusing ... - Jun 10
... VLSI Design Intern, 3D Ed Tech PVT. LTD. Jan 2022 – May 2022 • Applied Verilog HDL, Linux, and C programming for hardware design. • Acquired hands-on expertise in VLSI design methodology and FPGA optimization. • Specialized in FPGA design, focusing ... - Jun 10
Senior Manager R D
Pittsburgh, PA
... The rotations included Test Generation, System Level Machine Operation (Bring-up) for Systems Group, and High-Speed Microprocessor Design (ASIC VLSI Physical Designer). Education Marist College, Poughkeepsie NY – Major M.S., Information System ... - Jun 10
... The rotations included Test Generation, System Level Machine Operation (Bring-up) for Systems Group, and High-Speed Microprocessor Design (ASIC VLSI Physical Designer). Education Marist College, Poughkeepsie NY – Major M.S., Information System ... - Jun 10
Design Engineer Rtl
Hyderabad, Telangana, India
... Tech Mahindra, Bangalore Associate Engineer (VLSI) (Feb 2022 - March 2023) Designed and implemented FPGA IP cores such as FFT, FIR, and DDS using VHDL. Developed and verified FIFO designs using System Verilog testbenches. Worked on AMBA protocols ... - Jun 10
... Tech Mahindra, Bangalore Associate Engineer (VLSI) (Feb 2022 - March 2023) Designed and implemented FPGA IP cores such as FFT, FIR, and DDS using VHDL. Developed and verified FIFO designs using System Verilog testbenches. Worked on AMBA protocols ... - Jun 10