Fpga Engineer Hands-On

PRAPTI SHAH

279-***-**** **************@*****.*** linkedin.com/in/prapti-shah-71489b19a Sacramento – CA PROFESSIONAL SUMMARY

Versatile FPGA Engineer with 1.5 years of hands-on experience in FPGA development, specializing in Verilog HDL, RTL architecture, and FPGA toolchains such as Efinity, Vivado, and Quartus. Skilled in advanced methodologies including clock domain crossing (CDC), simulation, and synthesis for reliable hardware design. Proficient in designing and optimizing digital systems, incorporating DDR3 memory, AXI protocols, and SPI communication. Adept at FPGA workflows, including debugging, timing analysis, and performance enhancement. Passionate about cutting-edge FPGA research and eager to apply technical expertise to advance innovative hardware solutions through a summer internship.

EXPERIENCE`

FPGA Engineer, Vicharak PVT. LTD. Jan 2023 – Jun 2024

• Orchestrated AXI protocol for seamless UART-based data transmission.

• Engineered and fine-tuned Verilog HDL logic blocks to enhance computational efficiency.

• Prototyped and refined architectures on Efinix Trion-Series FPGAs (Vaaman SBC), performing iterative testing to ensure design accuracy and performance.

• Mastered DDR3 design, clock domain management, and performance tuning using Xilinx VIVADO and Efinity Toolchain for RTL verification, debugging, and comprehensive documentation.

• Implemented DDR3 memory with AXI protocol for efficient data handling, thereby ensuring seamless communication between memory and custom CPU architecture.

• Verified data storage integrity via UART, moreover conducted extensive timing assessments to identify and resolve negative slack and hold slack issues, leading to a 15% reduction in data latency.

• Enhanced the design in accordance with LUT allocation requirements provided by the team, whereas optimizing resource utilization by 10%.

• Deployed the DDR3 design on Efinix Trion-Series FPGA boards, followed by comprehensive debugging, which reduced system error by 25%.

• Constructed a robust UART system for uninterrupted 256-bit data transfer in 8-bit segments with zero data loss, which was utilized in DDR3 testing. The DDR3 module employed the AXI stream for efficient data passing. VLSI Design Intern, 3D Ed Tech PVT. LTD. Jan 2022 – May 2022

• Applied Verilog HDL, Linux, and C programming for hardware design.

• Acquired hands-on expertise in VLSI design methodology and FPGA optimization.

• Specialized in FPGA design, focusing on optimizing digital circuits for efficient implementation on Artix7 board.

• Architected an I2C interface using Verilog for streamlined hardware communication. SKILLS

Technical Tools : Efinity, Vivado, VITIS, Quartus prime lite, Modelsim, Xcelium, Virtual box, MATLAB, Proteus. Technical Language: Verilog HDL, VHDL, Basic knowledge of System Verilog, TCL, Linux, C Programming, Python. Hardware : Efinix Trion Series FPGA (T120F484, T85F484 FPGAs), Artix 7 FPGA, Intel DE-10 FPGA, Arduino UNO. Core Competencies: FPGA Design, RTL Design, Design Optimization, DDR design, AXI Protocols, Timing Analysis, Clock Domain

(CDC), Simulation, Synthesis, Debugging, SPI Design. EDUCATION

California State University, Sacramento Aug 2024 – May 2026 M.S., Electrical and Electronics Engineering (GPA-3.875) G H Patel College of Engineering & Technology, Anand, Gujarat July 2018 – May 2022 BE, Electronics and Communication Engineering (GPA-3.84) TRAINING/ COURSES

• Introduction to FPGA design for Embedded Systems – University of Colorado Boulder Expanded and extended design by integrating IP blocks, performing pin assignments, and generating FPGA programming files. Leveraged advanced design techniques such as pipelining and utilized Quartus Prime's Qsys tool to create a customizable NIOS II softcore processor, improving design productivity and enabling tailored processor development.

• Hardware Description Language for FPGA Design – University of Colorado Boulder Completed a course on Hardware Description Languages, where I developed proficiency in Verilog and VHDL for FPGA design. Gained hands-on experience in circuit design, language syntax, and testbench simulations to verify functionality.

• TCL Scripting – Training

Utilized Notepad++ and terminal utilities for basic automation and script execution. Strengthened a deep understanding of syntax, control flow, and procedural commands, boosting operational efficiency in FPGA environments.

• VLSI SoC design using Verilog HDL – Training MAVEN Silicon

• PCB Design – Internship

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