Design Engineer Hardware

Harshith Reddy Surakanti

Dublin, CA ********.*********@*****.*** +1-317-***-****

EDUCATION

Purdue University Indianapolis Indianapolis, IN

MS in Electrical and Computer Engineering (VLSI) Fall’2024 (GPA: 3.4) Coursework: SoC Design, MOS VLSI Design, ASIC Design Laboratory, Computer Architecture, Energy Conversion, Communication systems, Semiconductor TCAD (SILVACO). EXPERIENCE

Purdue University Indianapolis, IN

Primary GTA (ENGR 133) Fall’24

Developed in-class slides and assignments using Git for ENGR 133 Course at Purdue University.

Guided other GTAs, Graders and Collaborated with the instructor to enhance student learning using tools like Excel, Python, and MATLAB in Data Analytics, Encryption & Programming. Teaching Assistant (ECE 382) Spring’23, Fall’23

Controls system TA, led help sessions, evaluated assignments & exams, and conducted lectures. Integrated Test Range, DRDO Balasore, India

Hardware Design Engineer Intern 12/2021 – 11/2022

Designed RTL/IP modules, Overlays for Image processing & integrated hardware accelerators with Python.

Optimization of TCL automation scripts for PnR and STA. Documentation and guidelines creation for the team.

Gained hands-on experience in ASIC physical design including floorplanning, power planning, placement, CTS, and routing using Innovus; verified DRC/LVS, timing, and generated GDSII for tapeout. PROJECT WORKS

Karatsuba Multiplier Cadence Virtuoso

Designed 8x8 Karatsuba multiplier with True Single-Phase Clock (TSPC) logic in Cadence Virtuoso 45nm. Layout, DRC, LVS and Static Timing Analysis using NanoTime.

Documented the performance metrics with power dissipation of 242.556 uW and propagation delay of 796.886 pSec at 1GHz. Used 4486 transistors (1733 PMOS and 2752NMOS) resulting compact Layout. 8-Bit Manchester Adder Cadence Virtuoso

Implemented an 8-bit Manchester adder with pass transistor logic achieving significant improvements in propagation delay of 411.099 pSec and a power dissipation of 17.591 µW.

Focused on a minimalist approach, using only 208 transistors (26 per 1-bit adder) to lower Area and Power Consumption. Performed SPICE simulations along with AC, DC, and transient analyses. CUDA-Accelerated Parallel Computing Projects

Implemented multiple CUDA-based compute-intensive tasks, including Vector addition, Matrix multiplication, and Image convolution using custom CUDA kernels.

Developed CUDA kernels for parallel reduction, prefix sum (scan), and histogram computation.

Gained proficiency in optimizing memory access patterns using shared memory & thread blocks. MIPS Pipelined Processor with RAW hazard Resolution ASIC Physical Design, OpenLane

Designed & Verified 5-stage 32-bitpipelined MIPS processor using Verilog HDL in Xilinx Vivado 2024.2.

Implemented instruction-level parallelism & Integrated forwarding unit resolving RAW hazards.

Physical design is performed on OpenSource tools - Linting using Verilator, Yosys synthesis, openSTA, TritonCTS, openROAD for Floorplanning, Placement, Routing, Signoff & generated GDSII file for Tapeout. SKILL SET

Technical Skills: Verilog, SystemVerilog, Lint, VHDL, Linux, CUDA, TCL, Git, MATLAB, Python, C, SQL. Design Skills: Cadence tools – Xcelium, Genus, Innovus, Modus DFT, Virtuoso, OrCAD; OpenLane, Xilinx Vivado, Modelsim, Simulink and SILVACO TCAD.

Certifications : Cadence RTL-GDSII, Genus, Modus DFT/ATPG/MBIST.

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