Design Engineer Hardware

Harshith Reddy Surakanti

Dublin, CA ********.*********@*****.*** https://www.linkedin.com/in/harshith7/ https://github.com/HarshithR7 SUMMARY

Hardware Design Engineer with 3+ years’ experience in the industry with Proficiency in Verilog, VHDL, and SystemVerilog for digital design and verification, with expertise in RTL/IP, subsystem design and integration.

Skilled in TCL automation and Python for ASIC/SoC development. I have worked with Xilinx Zynq-7000 and Artix-7 boards, MIPS, RISC-V, and FPGA/SoC architectures. Eager to drive innovation into hardware design. EDUCATION

Purdue University Indianapolis Indianapolis, IN

MS in Electrical and Computer Engineering (VLSI) (GPA: 3.4) Graduation Date: 12/2024 WORK EXPERIENCE

Integrated Test Range, DRDO Balasore, India

Hardware Design Engineer 12/2020 – 11/2022

Designed and verified RTL/IP modules with a focus on FPGAs and SoCs, integrating IPs and hardware accelerators with Python running on embedded ARM cores, achieving a 40% reduction in latency.

Automated FPGA workflows using TCL scripts, with hands-on experience in both front-end and back-end tools. Performed linting, applied low-power design techniques, and STA, PnR, CDC and Routing checks. Successfully completed 3 tape-outs.

NTT Data GDS Bangalore, India

Senior Software Development Engineer 06/2019 – 12/2020

Enhanced ETL scripts for data extraction from SQL Server, improving data integration processes.

Designed, implemented, and maintained high-performance ETL workflows to ensure efficient data handling. Ensured data integrity and automation from multiple sources. PROJECTS

FPGA Custom IP Design and Hardware Acceleration Verilog, Python, IP design, SoC design, FPGA

● Developed custom IPs for Image filters, Image Resizing, Morphological operations and dynamic visual systems like moving block over background image.

● Accessing Hardware designs through Jupyter Notebook using python. Training visual datasets (MNIST, CIFAR) using ARM9 processing system speeding up the data processing 4x faster than software design. Dynamic Partial Reconfiguration of Image Filters on Pynq FPGA Board DPR, Verilog, TCL, Python

● Implemented Sobel, Sharpen, and Blur image filters on Pynq SoC using Verilog for PL and python for PS, creating reconfigurable logic with DPR technique.

● Automated the configuration process with TCL commands. Used python to enable seamless switching between filter configurations improving efficiency and studied bitstream manipulation techniques. MIPS Pipelined Processor with RAW hazard Resolution ASIC Design Flow, Physical Design, SDC

● Developed a 5-stage 32-bitpipelined MIPS processor in Verilog HDL. Implemented instruction-level parallelism and Integrated forwarding unit for resolving RAW data hazards.

● A custom DRC rule deck built using TCL and Linting using Verilator, Yosys synthesis, openSTA, TritonCTS,openROAD for Floorplanning, Placement, Routing, Signoff,GDSII file generated for Tapeout. 32-bit RISC-V processor with RV32I instruction set Computer Architecture, RISC-V, Verilog

● Developed a basic design of 5-stage pipelined 32-bit RISC-V processor using Verilog HDL implementing all addressing modes of RV32I instruction set architecture and Functional simulation verified. Design and Verification of FIFO memory FIFO, SystemVerilog, SVA, Coverage

● Executed multiple FIFO architectures - Shift Register, Exclusive and Concurrent Read /Write.

● Added memory depth and width depth extension through cascading multiple FIFOs. Created a test plan and verified scenarios using SystemVerilog Assertions for TI SN74ACT7807. SKILLS SET

● Technical Skills: Verilog, SystemVerilog, Lint, VHDL, CUDA, TCL, Git, MATLAB, Python, C, SQL.

● Design Skills: Cadence Virtuoso, Innovus, Nanotime, Xilinx ISE, Modelsim, Simulink and TCAD.

● Protocols: I2C, SPI, AMBA- AXI4, UART, USB.

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