Design Engineer Rtl

NAGA BABU KILADI

RTL Design Engineer

Hyderabad, India 500032

LinkedIn: https://www.linkedin.com/in/nagababu028/ Phone: 901-***-****

Email: **************@*****.***

Objective

Results-driven RTL Design Engineer with over 3 years of experience in RTL coding, IP development, and high-speed digital interfaces. Seeking a challenging role where I can leverage my expertise in RTL design, verification, and debugging to contribute to innovative projects. Technical Skills

Programming Languages: Verilog,VHDL, System Verilog

Tools: Xilinx Vivado, Modelsim, Chipscope, MATLAB, Synopsys VCS

Protocols: AHB, APB, UART, SPI, I2C, Ethernet, GTX Transceivers, SERDES

High-Speed Interfaces: DDRx, ADC, DAC, USB, JeSD

Verification Methodologies: UVM, System Verilog Testbenches

Scripting Language: TCL

Professional Experience

Unistring Tech Solutions, Hyderabad

RTL Design Engineer (May 2023 - Present)

Designed and implemented RTL code in VHDL and Verilog for FPGA-based product development.

Developed and tested high-speed transceiver interfaces on Xilinx 7045 FPGA.

Implemented drone jamming and GNSS spoofing algorithms for GPS L1, GALILEO E1, and BEIDOU B1, achieving a 30% improvement in signal accuracy.

Conducted static timing analysis and resolved timing issues in high-speed designs.

Validated algorithms using MATLAB and UBLOX receivers for real-time testing.

Designed and implemented efficient power optimization techniques for FPGA-based designs.

Worked on RTL synthesis and floorplanning for complex FPGA projects. Tech Mahindra, Bangalore

Associate Engineer (VLSI) (Feb 2022 - March 2023)

Designed and implemented FPGA IP cores such as FFT, FIR, and DDS using VHDL.

Developed and verified FIFO designs using System Verilog testbenches.

Worked on AMBA protocols (AHB, APB) and designed AHB-to-APB bridges.

Conducted verification using UVM testbenches for complex designs. Projects

Counter Drone System (ISM Band Detection Receivers, Jammers, Spoofers)

Developed ISM band jamming techniques (Spot, Sweep, Barrage) for drone detection.

Implemented GNSS spoofing algorithms for GPS L1, GALILEO E1, and BEIDOU B1.

Validated spoofing algorithms using UBLOX receivers and MATLAB simulations.

Performed static timing analysis and resolved timing issues.

Debugged hardware using Chipscope Analyzer and Spectrum Analyzer. PMDL (Passive Multi Drone Locator)

Developed and implemented algorithms for passive multi-drone detection.

Interfaced DAC/ADC daughter cards with Zynq FPGA using Vivado.

Designed RX signal detection and phase synchronization for 8 channels.

Verified functionality at the hardware level on FPGA using Vivado.

Resolved static timing analysis (STA) and clock domain crossing (CDC) issues. C & X Band Radar Target Simulator

Designed and implemented digital beamforming techniques for radar target simulation.

Developed range simulations, Doppler effect, and RCS variations.

Implemented memory-based DRFM (Digital Radio Frequency Memory) techniques.

Verified radar signals using Spectrum Analyzer and Chipscope.

Optimized FPGA timing to improve real-time performance. Image Fusion Techniques for Camera Modules

Designed and implemented image fusion algorithms in Xilinx Vivado for FPGA-based camera modules.

Developed image processing algorithms in Verilog to enhance real-time video processing capabilities.

Integrated multiple sensor data streams and implemented efficient fusion techniques for improved image clarity.

Implemented scaling, histogram equalization, and edge detection algorithms in Verilog for enhanced image quality.

Designed image scaling, contrast enhancement, and multi-resolution fusion techniques in Verilog.

Optimized timing issues, improving processing speed by 15%.

Conducted verification using System Verilog testbenches and FPGA simulation tools.

Debugged and optimized RTL logic to improve power efficiency and processing speed. Education

Bachelor of Technology (B.Tech), Electronics and Communication Engineering Andhra University, Visakhapatnam (July 2019 - May 2022) CGPA: 8.7 Diploma in ECE

Government Polytechnic College, Vijayawada (June 2016 - May 2019) CGPA: 9.3 Certifications

Digital System Design - Tech Mahindra

Verilog Foundation - Tech Mahindra

System Verilog Foundation - Tech Mahindra

AMBA APB in Verilog - Namaste FPGA

Achievements

Successfully implemented GNSS spoofing algorithms, improving signal accuracy by 30%.

Optimized timing issues in complex designs, enhancing processing speed by 15%.

Developed ISM band jamming techniques, reducing drone detection time by 20%. Languages

English: Professional Proficiency

Telugu: Native

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