Design Engineer Security Clearance

STEPHEN KOUBEK

Huntsville, AL *****

*******@*****.*** 256-***-**** www.linkedin.com/in/stevekoubek

SENIOR HARDWARE DESIGN ENGINEER

Drive Productivity Manage Teams Improve Processes Deliver Results On Time & Within Budget Active Security Clearance (TS)

Experienced in system architecture design, digital design, and simulation of application-specific integrated circuits (ASICs), printed circuit boards (PCBs), multi-chip modules (MCMs), and field-programmable gate arrays (FPGAs). Conduct proposal research, design reviews, test, integration, and documentation. Translate technical information into clear, understandable, and actionable steps for team member application.

ASICs Intellectual Property (IP) Development, Integration, & Qualification Telemetry System Design & Development Verification Test Bench Development & Writing Tests System Bus Architecture Design & Development Synthesis Using Synopsys & Cadence Tools Printed Circuit Board Design Analog Circuit Design Hardware Design Using Verilog & VHDL Universal Verification Methodology (UVM) TECHNICAL SKILLS

Tools – Mentor: Questa Prime and Questa AutoFormal Tools – Cadence: All Cadence digital simulation tools, including NCSim and regression tool Vmanager Tools – Synopsys: Primetime, Design Compiler, Physical Compiler, Tetramax, Formality, Spyglass, coreAssembler, and coreBuilder

FPGAs: Xilinx, Altera, Microsemi, and Lattice parts and tools Operating Systems: Linux and Unix

Languages: C programming, Python, Perl, and tcl scripting PROFESSIONAL EXPERIENCE

People Tec, Incorporated, Huntsville, AL 2024 – Present Senior FPGA Design Engineer

Design, verification and synthesis of digital systems and IP working as an embedded contract engineer for DoD customer.

IP development and testing.

Developed testbenches and simulation environments for verification and system integration.

Work closely with team members for successful delivery. Radiance Technologies, Huntsville, AL 2021 – 2024

Senior ASIC Design Engineer

Design, verification and synthesis of digital systems and IP working as an embedded contract engineer for DoD customer.

Completed all design projects within schedule, working closely with team members for successful delivery.

Developed testbenches and simulation environments for verification and system integration.

Responsible for selection and maintenance of tools. Invariant Corporation, Huntsville, AL 2016 – 2021

Senior Design Engineer

Design, verification and synthesis of digital systems and IP working as an embedded contract engineer for DoD customer.

Completed all design projects within schedule, working closely with team members for successful delivery.

Developed testbenches and simulation environments for verification and system integration.

Responsible for selection and maintenance of tools. ST MICROELECTRONICS, (formerly CISCO / SCIENTIFIC ATLANTA), Huntsville, AL 2001 – 2016 Senior Hardware Design Engineer

Designed ASICs for digital set-top boxes and home gateway system on a chip (SOC). Provided primarily register-transfer level

(RTL) design, IP integration, verification, and IP validation for delivery.

Completed all design projects within cost and schedule, facilitating design integration into millions of products worldwide.

Validated Docsis3.1 IP by performing final RTL checks using Spyglass, BIST (Built in Self-Test) insertion, synthesis, constraints generation, test insertion, test pattern generation, timing analysis, and formal verification, delivering to back- end team for placement and routing.

Resolved timing and congestion issues, addressing all RTL specific concerns communicating effectively with team members.

Designed system bus architecture for numerous ASICs and IP, including 50M gate Docsis headend ASIC, Docsis3.1 and Docsis3.0 IPs, and developed bus architecture for FPGA prototype SOC platforms, encompassing memory map development, generating and developing RTL, simulating, verifying, and documenting.

Provided test bench development for several ASICs and IP, writing several detailed tests for verification of sub-modules and top-level system.

Verified complex IP using Cadence’s Vmanager by developing tests for verification of Docsis3.0 multi-channel upstream / downstream and using functional coverage as “completion” metric.

Facilitated key IP component integration and testing for video pipeline in set-top box ASICs, including dual H.264 / MPEG- 4 video decoders, ARM Mali graphics core, and Blitter functions. Video decoders and ARM graphics core had multiple embedded processors.

LOCKHEED MARTIN AT NASA / GSFC, Greenbelt, MD 1993 – 2001 Senior R&D Engineer

Conducted research and development of new technologies, architectural and logic design, simulation, test, and characterization of very-large-scale integrated (VLSI) circuits required for high speed / low cost space and ground systems. Supervised team of 5-10 engineers, based on project perimeters.

Lead Hardware Engineer for next generation all-digital 600 Mbps receiver. o Designed 5M transistor .35-micron ASIC that demodulated BPSK and QPSK data at rates up to 600 Mbps. o Assisted with 1.2 GHz GaAs Multiplexer ASIC and high rate Viterbi decoder ASIC design, with 300 Mbps data rates. o Simulated 3 ASICs as a system and integrated onto PCI compatible card, completing receiver system. o Coordinated implementation and development of digital signal processing (DSP) algorithms into actual hardware elements, prototyping algorithms in hardware using FPGAs.

Lead Hardware Engineer for ATM conversion device (ACD) project. o Designed and developed all hardware and system allowing ECL and RS-422 end-to-end data transmission. o Led and coordinated all system integration and software tasks. o Designed Motorola 68030 based VME card, providing ECL and RS-422 serial interface to ATM network.

Designed MCM utilizing Anti-Fuse technology substrate and reconfigurable logic, allowing wide variety of applications. o Researched and evaluated different MCM technologies and vendors, selecting best suited for project.

Designed Motorola 68030 CPU mezzanine board, used as embedded processor on motherboard designs.

Member of Hardware Environment Group: handled all hardware-related issues, including evaluating and upgrading of new design tools and continual improvement of entire in-house design environment. EDUCATION

Bachelor of Science (BS), Electrical Engineering, University of Nebraska-Lincoln, Lincoln, NE PUBLICATIONS

"Return Link Processor Card", NASA Tech Briefs, 1999.

"High Rate Digital Demodulator ASIC", International Telemetry Conference, 1998, International Conference on Signal Processing and Technology, 1998.

HONORS AND AWARDS

Lockheed Martin Merit Award: outstanding performance

NASA Certificate of Appreciation: Goddard and NOAA Programs

NASA Certificate of Recognition: creative development of technical innovation (proposed for NASA Tech Brief publication entitled: “Return Link Processor Card")

Golden Key National Honor Society

Alpha Lambda Delta and Phi Eta Sigma Honor Societies

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