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Resumes 91 - 100 of 510 |
San Jose, CA
... circuits, Advance Microwave Engineering, Mobile Communication systems, Digital Logic Design, Microprocessors and Microcontrollers SKILLS § Tools: Calibre PV tools, Cadence Virtuoso, Xilinx ISE, Vivado, LTSpice, Advance Design System (ADS), ModelSim. ...
- 2019 Aug 27
Sunnyvale, CA
... • Experience in using Cadence, Synopsys various VIPs and deployment • Experience in IP/block/SOC level verification. • Expertise in development of UVM/OVM compliant coverage driven randomized Test bench environment using System Verilog & SVA • ...
- 2019 Jul 10
Pleasanton, CA
... Tracked issues, risks, metrics, took corrective & preventive actions, drove results on a regular cadence. Resolved issues post deployment, partnering with ServiceDesk / HelpDesk, Virtual Support, Technical groups. SYMANTEC CORPORATION, Mt. VIEW, CA ...
- 2019 Jun 20
Fremont, CA
... Can use PCAD-2001, Solid-Works and Cadence CAD tools. MS Outlook, Word, Excel, VISIO, OMNIGraffle Apple Inc. 10/2009 – 04/2019 RF Lab Manager/Technician Built, expanded, maintained and supported RF compliance and certification test labs for all ...
- 2019 May 21
Foster City, CA
... India, GPA – 8.7 / 10.0 Jul ‘07 - May ‘11 TECHNICAL SKILLS Programming - C, Matlab/Simulink Software – Simplis, LTSpice, Cadence Virtuoso, Altium, MathCAD, Orcad, Git ACHIEVEMENTS Recipient of $4k Gates fellowship Jan ’18 – May ‘18 Recipient of ...
- 2019 May 16
San Jose, CA
... TECHNICAL SKILLS Languages and/or HDL - Verilog, System Verilog, Perl, C++ EDA Tools - Synopsys VCS, Cadence Incisive, NCSim, Virtuoso, Spectre, Hspice, Xilinx ISE, ModelSim Operating Systems - Linux, Windows, macOS Familiarities – ASIC/FPGA design ...
- 2019 May 14
Milpitas, CA
... (Altium17.1.9 and Cadence Allegro 17.2 and Solidworks) Flex designs and manufactures for all kinds of customers who provide data in different CAD packages. I am proficient in both Allegro, Altium and Solidworks. Square Inc. January 2014 – March 2017 ...
- 2019 Apr 09
San Jose, CA
... Tools Verilog Cadence- Virtuoso DSP Builder System Verilog Synopsys- Design Vision Matlab C Quartus II Comsol R Low Power Solution ModelSim Python Synopsys- Design Complier RESEARCH PROJECTS The George Washington University, Washington, DC Oct. ...
- 2019 Apr 05
San Jose, CA
... EXPERIENCE CADENCE DESIGN SYSTEMS, San Jose, CA 1999 - 2018 Dec. Senior Staff Systems Engineer 2005-2018 : Designed and managed IT UNIX/Liunx infrastructure to meet the capacity and change requirement for global operation and new development needs ...
- 2019 Feb 06
Castro Valley, CA
... provided oversight for the development and maintenance of quality programs, systems, processes and procedures that ensure compliance to established regulations and standards Provided cadence of communication to executive team for project updates and ...
- 2019 Jan 18