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Engineer Test

Sunnyvale, California, United States
July 10, 2019

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Kumaraswamy V.


Email: Mobile: 408-***-****

• Strong technical expertise with hands on and leadership skills.

• 10+ Yrs. of experience in design verification of various complex ASICs from concept to silicon.

• Experience in ASIC verification, VIP development, Board bring-up, FPGA Emulation and System validation of embedded system.

• Experience in verifying the Storage, DSP, Video, Consumer Electronics/Multimedia, Wireless domain ASICs

• Worked with cross-functional groups and multi-geographical locations

• Strong debugging skills.

Technical Experience

• Protocol knowledge in PCIE (TL, DL, PL) layers, LPDDR4/DDRPHY (QFI), USB, MIPI-MPHY, HDMIPHY, I2C, SPI, AHB.

• Test plan creation, RC based PCIE tests creation, end2end simulation to verify the PCIE device controller.

• RTL simulation & debug on DDRCC IP verification.

• Experience in using Cadence, Synopsys various VIPs and deployment

• Experience in IP/block/SOC level verification.

• Expertise in development of UVM/OVM compliant coverage driven randomized Test bench environment using System Verilog & SVA

• Experience in developing and executing the test plan for the verification of ASIC, develop and maintain test environment, test automation, LSF, methodology, make files, tools, and scripting.

• Familiar with industry standard simulation tools IUS, VCS Questa and debuggers: DVE, VERDI, SIMVISION.

• Good Experience in RTL & Gate level simulation with SDF annotation & debug, analysis of RTL code coverage, and functional coverage model development

• Experience in test scenarios creation for C/C++ based verification environment, PROFESSIONAL EXPERIENCE

11/2018 to till date Verification Lead Synapse Design Responsibilities

• Gate level simulation & debug of CPU core for different phases of netlist

• Develop and maintain the GLS flow

• SVA assertions to check the core bring-up sequence in PAGLS.

• RTL simulation and debug on CPU core to verify the various registers behaviour during CPU execution and developed the checkers to verify the registers behaviour against microcode 02/2018 to 11/2018 Verification Lead Synapse Design Responsibilities

• Lead the Verification activity at MegaChips for ARM based SOC verification of the Video Protocol Converter ASIC

• Prepare the Test plan and Verify the features of the Video IP, video scalar, Routing logic at the SOC level and MFP functionality

• Chip level tests creation using C to verify the CSC (colour space converter) block in SOC level, reference model integration & debug

03/2017 to till 01/2018 Senior Verification Engineer Exmius Design Responsibilities –

• Feature list Creation and Exercise Test plans for the verification of sequencer based 25G SERDES PHY which supports multiple PHY protocols

• protocol layer enablement with Mentor VIP to verify the PCIE controller with the SERDES and simulation of PCIE packets from/to protocol layer & phy layer

• Developed tests/sequences to verify different blocks of SERDES PHY using UVM system Verilog

• RTL failure analysis and debug, simulations and closure on RTL failures, Gate level simulation

• Lead and mentor the junior engineer for the verification activity and co-ordinate the verification tasks in different geographical locations.

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Kumaraswamy V.

07/2015 to 02/2017 Senior Technical Lead Aricent Inc Responsibilities – Verification of DDRPHY for LPDDR4 at core level

• Familiarize with DDRPHY/DDRCC, QFI, MCCC, LPDDR4 specification

• Understand the existing the Test Bench framework and infrastructure.

• Created the tests and sequences to verify the DDRCC/DDRPHY which contains Denali model LPDDR4 memory interface and QFI1.1 protocol interface

• Developed and maintain the Test bench infrastructure and Test Plan creation, white box DDRCC and DDRPHY SVA assertions

• RTL failure analysis and debug functional failures and support for chip and bench level issues

• Coverage model development and analysis of code and functional coverage, achieve functional/code coverage metrics on DDRCC/DDRPHY

• Executed Gate level simulations (with and without SDF) and power aware (RTL/GLS) simulations 07/2014 to 06/2015 Senior Technical Lead Aricent Inc Responsibilities – Verifying the programmable Gigabit Transceiver at quad level

• Understanding the existing advanced multi-layered Quad level UVM test environment

• Created tests/sequence for the QUAD Serdes IP for the verification of the GT includes Quad configuration. Clocking, RCAL, ACJTAG and other data path functional blocks.

• Developed and maintain the Quad level UVM test environment and the verification flow 06/2012 to 06/2014

Responsibilities Senior Verification Engineer Aricent Inc

• Familiarize with the MPHY & UFS controller specification,

• Developed and executed the UFS MIPI-MPHY test plan, Block level MPHY DV verification setup include integration of the CADENCE VIP, protocol specific sequence creation.

• Test Case development for the MPHY TX data path, MIPI controller interface module and BIST interface module, RTL simulation, failure analysis and debug.

• SVA assertion development to verify the internal RTL signals. of SERDES and MIPI_PHY PCS, connectivity assertion on all Analog macros

• SOC verification support for the MPHY block and characterization tests,

• Functional coverage and code coverage analysis and closure of functional and code coverage holes

• Familiarize with the HDMI PHY specification, Test Bench development to verify the HDMIRXPHY IP, RTL simulation, failure analysis & debug

01/2011 to 05/2012 Senior Verification Engineer Synapse Design Responsibilities

• Test plan creation for Interpolator and Resampler modules of a DSP049 ASIC block level verification for the test instruments platform

• Implemented the OVM system Verilog testbench components to verify memory controller interface, DPI (Direct programming Interface) module to interface system Verilog and C based MATLAB model integration.

• OVM based system Verilog Test case creation, logic simulation, RTL failure analysis and debug on INTERP block

• Implemented the randomized constraint module, coverage model development, code and functional coverage analysis, achieve coverage metrics

• QuestaSim/MATLAB tools were used for the simulations. SVN was used for version control. 3 P a g e

Kumaraswamy V.

12/2006 to 12/2010 Technical Lead MindTree Limited Responsibilities

• Architect and developed a verification plan for the PCIE Root Complex eVC to verify the PCIE Device Controller, responsible for complete verification activity.

• Development of checkers for the transaction and Datalink layers, Debug and simulation of end to end PCIE packets

• Execute Test plan to verify the PCIE device controller using PCIE eVC, RTL simulation/debug and eVC Debug.

• Creation of tests to Verify the PCIE subsystem in the wireline chipset, logic simulation, RTL failure analysis and Debug.

• TB development for DDR2 controller, temporal checkers to check the timing violations from DDR2 controller verification

• Test creation in E, RTL simulation & debug to verify the DDR2 controller

• Execute test plan to Verify the EMF module at the SOC level, RTL simulation & Debug

• Coverage specification and analysis.

10/2003 to 11/2006 Senior Engineer Wipro Technologies Responsibilities

• Test plan & feature extraction for the RIO router and the IO pipe module of BOSCO DMA chip set

• Created test cases in C++ and verify the RIO router and IO pipe modules in Tensilica based SOC.

• Develop a verification plan for CONPRO (Content Protection ARM SOC)

• Architected and created the test bench infrastructure to verify the CONPRO SOC for RTL/Gate level simulation

• Tests creation, logic simulation, RTL failure analysis and debug on CONPRO block.

• Code coverage analysis, gate level simulation with SDF

• ARM7 DSM and peripheral design IPs integration. h/w s/w Co-simulation setup creation.

• Created the test plan for the HIU module for gaming chipset ASIC

• Created the test bench components in specman E to verify HIU block, logic simulation, RTL debug

• Created tests in Specman E to verify the EMC module (external memory controller) in gaming chipset ASIC

• SOC level verification by generating PCI/PCIE DMA transaction in the host data path,

• Verify the HIU using PCIE/PCI packets generation using SNPS VIP. EDUCATION

• Highest Degree Held: Bachelor of Electrical Engineering (Instrumentation) from University of Mysore.

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