| Distance: | Resume alert | Resumes 11 - 20 of 6502 |
Operations Center Network
Orlando, FL
... Accomplished functional design for VLSI integrated circuits. Performed stress analysis, Worst-case timing analysis. Security Clearance level – Secret Resume’ -- Herbert A. Teague SPECIAL SKILLS/EXPERTISE NOC Tech ATM Network Surveillance and Repair ... - Jun 13
... Accomplished functional design for VLSI integrated circuits. Performed stress analysis, Worst-case timing analysis. Security Clearance level – Secret Resume’ -- Herbert A. Teague SPECIAL SKILLS/EXPERTISE NOC Tech ATM Network Surveillance and Repair ... - Jun 13
Design Engineer Hardware
Dublin, CA
Harshith Reddy Surakanti Dublin, CA ********.*********@*****.*** +1-317-***-**** EDUCATION Purdue University Indianapolis Indianapolis, IN MS in Electrical and Computer Engineering (VLSI) Fall’2024 (GPA: 3.4) Coursework: SoC Design, MOS VLSI Design, ... - Jun 11
Harshith Reddy Surakanti Dublin, CA ********.*********@*****.*** +1-317-***-**** EDUCATION Purdue University Indianapolis Indianapolis, IN MS in Electrical and Computer Engineering (VLSI) Fall’2024 (GPA: 3.4) Coursework: SoC Design, MOS VLSI Design, ... - Jun 11
Systems Engineer Computer Engineering
San Diego, CA
Aghared Shaba San Diego, CA *********@*****.*** LinkedIn: Aghared Shaba GitHub: aghared Summary Recent Computer Engineering graduate knowledgeable in digital systems design, embedded systems, and VLSI. Familiar with Verilog, C, C++, Python, and Java ... - Jun 11
Aghared Shaba San Diego, CA *********@*****.*** LinkedIn: Aghared Shaba GitHub: aghared Summary Recent Computer Engineering graduate knowledgeable in digital systems design, embedded systems, and VLSI. Familiar with Verilog, C, C++, Python, and Java ... - Jun 11
Fpga Engineer Hands-On
Sacramento, CA
... VLSI Design Intern, 3D Ed Tech PVT. LTD. Jan 2022 – May 2022 • Applied Verilog HDL, Linux, and C programming for hardware design. • Acquired hands-on expertise in VLSI design methodology and FPGA optimization. • Specialized in FPGA design, focusing ... - Jun 10
... VLSI Design Intern, 3D Ed Tech PVT. LTD. Jan 2022 – May 2022 • Applied Verilog HDL, Linux, and C programming for hardware design. • Acquired hands-on expertise in VLSI design methodology and FPGA optimization. • Specialized in FPGA design, focusing ... - Jun 10
Senior Manager R D
Pittsburgh, PA
... The rotations included Test Generation, System Level Machine Operation (Bring-up) for Systems Group, and High-Speed Microprocessor Design (ASIC VLSI Physical Designer). Education Marist College, Poughkeepsie NY – Major M.S., Information System ... - Jun 10
... The rotations included Test Generation, System Level Machine Operation (Bring-up) for Systems Group, and High-Speed Microprocessor Design (ASIC VLSI Physical Designer). Education Marist College, Poughkeepsie NY – Major M.S., Information System ... - Jun 10
Design Engineer Rtl
Hyderabad, Telangana, India
... Tech Mahindra, Bangalore Associate Engineer (VLSI) (Feb 2022 - March 2023) Designed and implemented FPGA IP cores such as FFT, FIR, and DDS using VHDL. Developed and verified FIFO designs using System Verilog testbenches. Worked on AMBA protocols ... - Jun 10
... Tech Mahindra, Bangalore Associate Engineer (VLSI) (Feb 2022 - March 2023) Designed and implemented FPGA IP cores such as FFT, FIR, and DDS using VHDL. Developed and verified FIFO designs using System Verilog testbenches. Worked on AMBA protocols ... - Jun 10
Business Development Product Marketing
Orlando, FL, 32885
... Solid understanding of technical issues, especially in multimedia and communications VLSI products. Healthy, fit, well groomed personality Personal attributes include a high energy level, self-motivation, sense of humor, ability to accept delegation ... - Jun 09
... Solid understanding of technical issues, especially in multimedia and communications VLSI products. Healthy, fit, well groomed personality Personal attributes include a high energy level, self-motivation, sense of humor, ability to accept delegation ... - Jun 09
Assistant Professor Service Engineer
Muscat, Muscat Governorate, Oman
... VLSI Design 4. Linear Integrated Circuits 5. Electronic Devices & Circuits (2Times) 6. Communication Theory (3Times) 7. Power Electronics 8. Digital Signal Processing 9. Control Systems LABORATORY HANDLED UG 1. Digital Electronics Lab 2. VLSI Design ... - Jun 07
... VLSI Design 4. Linear Integrated Circuits 5. Electronic Devices & Circuits (2Times) 6. Communication Theory (3Times) 7. Power Electronics 8. Digital Signal Processing 9. Control Systems LABORATORY HANDLED UG 1. Digital Electronics Lab 2. VLSI Design ... - Jun 07
Design Engineer Senior
Los Gatos, CA
... Rensselaer Polytechnic Institute, Troy, New York 1991–1997 MS in EE (VLSI focus) in 1996. BS in EE obtained in 1995, graduated Summa Cum Laude. - Jun 05
... Rensselaer Polytechnic Institute, Troy, New York 1991–1997 MS in EE (VLSI focus) in 1996. BS in EE obtained in 1995, graduated Summa Cum Laude. - Jun 05
Electrical Engineering A M
College Station, TX
... IEEE Publication - “Multi-Threshold CMOS Devices: A Comparative Analysis of Leakage Power…” – 2019 [For ASIC] COURSE WORK ECEN 665 - RF Integrated Circuits and Systems (Unofficial) - ECEN 704 – VLSI Circuit Design, ECEN 607 – Advanced Analog Design, ... - Jun 03
... IEEE Publication - “Multi-Threshold CMOS Devices: A Comparative Analysis of Leakage Power…” – 2019 [For ASIC] COURSE WORK ECEN 665 - RF Integrated Circuits and Systems (Unofficial) - ECEN 704 – VLSI Circuit Design, ECEN 607 – Advanced Analog Design, ... - Jun 03