Design Engineer Senior

tel. +1-408-***-****

email: ******@*****.***

SENIOR DESIGN ENGINEER

Innovator, Writer and Lecturer in the Semiconductor Industry.

TIMING ANALYSIS & PHYSICAL DESIGN

• Structural RTL code for optimal area and timing closure in synthesis.

• Structured datapath design with TCL and Innovus.

• Custom standard cell design for optimum PPA (custom logic, flip-flops, anti-glitch gated drivers).

• Reusable memory periphery cell design for memory compilers and custom RAMs.

• IR Drop, EM, and physical verification in advanced technology nodes.

• Block level floor planning and power grid planning.

• Full chip signal planning – repeater and latch/flop placement, metal layer and route definition.

• Block level clock distribution, skew minimization and clock gating.

• Chip level clock transmission across power domains, custom level shifter for minimal clock skew.

• Timing closure and STA sign-off.

• Experience with timing flows and timing constraints & exceptions for industry standard tools.

• Experience in STA for high performance CPU designs.

• Timing analysis with memories (full swing and differential).

• Timing closure for multi-clock domain designs.

• Timing analysis with multiple timing corners and worst case corner selection.

• Timing analysis for maxtime (slowest paths), and mintime (fastest paths).

• Self-timed and frequency dependent margin analysis using Nanotime and Ultrasim.

• Statistical simulations for POCV (parametric on-chip variation) modeling in Nanotime.

• Timing correlation between STA tools and high speed Spice simulators across process corners.

• Experience with time borrowing concepts and extensive use of bi-directional time borrowing circuits.

• Implementation and validation of timing constraints & exceptions (SDCs):

• For proper signal propagation through edge shaping circuits like clock choppers (false paths).

• For proper signal propagation through clock gating circuits and clock dividers.

• For proper timing analysis with weak devices such as keepers or memory cells.

• To limit simulations through similar paths (like wordlines in SRAM).

• Setup and hold Spice sweep simulations for custom Flip-Flops and latches.

• LVF (liberty variation format) timing model generation for setup and hold in multiple corners.

• Experience with hand-crafted timing models for flow-through, latch based timing paths.

• Noise analysis with tools like Nanotime and in-house tools.

• Experience in working with cross functional teams, including CAD, to implement timing and noise analysis infrastructure.

• Experience with timing and noise methodology definition and documentation.

TECHNICAL CONSULTING (2017-2020)

Cornami, Circuit Design Consultant (contract), Campbell, CA 10/19–03/20

Design environment setup, dynamic circuit design, memory feasibility analysis.

About The Kids Foundation, Researcher (contract), Los Altos, CA 01/19–09/19

Mathematics work with the intent to create a better software tracking system for missing children.

Wave Computing, Senior Design Engineer (contract), Campbell, CA 03/18–11/18

SRAM memory verification, design completion, timing and back-end analysis.

AMD / Invecas, Senior Timing Engineer (contract), Sunnyvale, CA 07/17–12/17

Nanotime timing analysis on SERDES units, focusing on CMOS PLL clock dividers.

FULL TIME TECHNICAL (1996-2023)

Micron, Senior DRAM Design Engineer, GA/CA 2022–2025

Design and optimization of HBM memory/logic/analog circuits.

Broadcom, High Speed Memory Design Engineer, MN/CA 2021–2022

SRAM memory circuit design, memory compiler flow, timing and back-end analysis.

Intel Corporation, Senior Circuit Design Engineer, Santa Clara, CA 2016–2017

Standard cell design, structured datapath design, timing methodology (processor and SoC).

Soft Machines (acquired by Intel), Circuit Design Engineer, Santa Clara, CA 2014–2016

Custom circuit design, memory & register file design, clock and noise methodology.

Nvidia Corporation, Senior Memory Design Engineer, Santa Clara, CA 2009–2013

Cache memory design for high performance & low power ARM processor IP.

Sun Microsystems, SRAM Design Engineer, Sunnyvale, CA 2000–2009

SRAM memories (6T & 8T), multi-cycle signaling, noise methodology for SPARC processors.

ATMOS, IP Design Engineer, Canada/Poland 1998–1999

Redesigned IP library cells for compiler generated RAM, based on customer needs.

Silicon Graphics, Design Engineer, Mountain View, CA 1996–1998

Custom circuit design and verification on memory sub-blocks for MIPS processors.

TEACHING & PUBLICATIONS (2011-Present)

Teaching & Publishing, Course Developer & Writer, Campbell, CA 03/20–Present

Work on my next book & course: Distributed Dynamic Circuits and Full Swing Memory Design.

Seico Epson, Technical Writer, Campbell, CA 01/21–03/21

Whitepapers on timing, power, oscillator design & crystal manufacturing for Real Time Clocks.

San Jose State University, Professor, San Jose, CA 05/17–12/19

Lectured on “Electronics for Computing Systems”, a hardware design course (CMPE110).

Teaching & Publishing, Course Developer & Writer, Campbell, CA 2017–2018

Online course (Udemy/Linda): “Learn How to Design Electronics for Computer Systems”, 2018.

Teaching & Publishing, Writer, Campbell, CA 2011–2012

Book on dynamic circuit design entitled “Synchronous Precharge Logic”, Elsevier Insights, 2012.

PATENTS

US 201********:

Column select multiplexer and method for SRAM and computer memory subsystem.

Active column mux for improved bitline read time.

US 1-999-***-****:

Method and circuitry for soft fuse row redundancy with simple fuse programming.

Methodology around simple fuse programming.

US 1-999-***-****:

Method and circuitry for soft fuse row redundancy with simple fuse programming.

Circuit solution to easy soft (MOS) fuse programming used in row redundancy.

Note: Other patents filed and pending.

ENTREPRENEURAL ACTIVITY (2017-2020)

ZUMI Computer Systems, Founder, Campbell, CA 2017–2020

Co-founded a company to simplify computing for clients such as: small businesses, medical offices, schools, homes, and others.

The idea was to leverage pre-existing hardware and software, with minimum investment in new development to reduce cost and time to market. Because other companies’ technology was licensed and used extensively, we were not creating competition for them – we would in fact enhance their bottom line. It was a superb learning experience.

Business plan, roadmap development and technical presentations.

Technical development scope:

oHardware focus: USB interface for smart-card/NFC virtual account storage.

oSoftware focus: Code for hypervisors, cloud data storage and account authentication.

Meetings with numerous successful startup entrepreneurs.

Meetings with many potential clients for market research.

Meetings with venture capital investors.

Meetings with computing industry decision makers.

Stanford Startup Course from Y Combinator.

Note: Full details of all my technical work, innovation and leadership can be found on my LinkedIn profile: https://www.linkedin.com/in/marek1/

EDUCATION

Princeton University, Online Education 2015

Neuroscience of Everyday Life, a brain science course with Associate Professor Sam Wang, Ph.D.

University of California, Berkeley, California 2013

Leadership professional program.

De Anza College, Cupertino, California 2011

Courses in C, C++, Shell scripting and Perl.

Stanford University, Palo Alto, California 1997–2000

Graduate courses in digital and analog integrated circuits (20 units, certificates).

AGH University of Science and Technology, Kraków, Poland 1994

Courses in digital electronics, logic design, and computer architecture (exchange programme).

University of Sussex, Brighton, England 1993

Courses in analogue electronics, EEPROM programming, PCB lab (exchange programme).

Rensselaer Polytechnic Institute, Troy, New York 1991–1997

MS in EE (VLSI focus) in 1996. BS in EE obtained in 1995, graduated Summa Cum Laude.

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