| Distance: | Resume alert | Resumes 81 - 90 of 6087 |
Design Verification
Washougal, WA
... GPA:3.63/4 • Coursework: Microprocessor System Design, ASIC Modeling & Synthesis, Intro to System Verilog, Computer Architecture, Pre-Silicon Validation, Assertion based Verification, SoC Design with Programmable Logic, Formal Verification G. ... - Mar 23
... GPA:3.63/4 • Coursework: Microprocessor System Design, ASIC Modeling & Synthesis, Intro to System Verilog, Computer Architecture, Pre-Silicon Validation, Assertion based Verification, SoC Design with Programmable Logic, Formal Verification G. ... - Mar 23
Hardware Security Ic Design
Santa Clara, CA, 95054
... Languages: Verilog, TCL, VHDL, Python, C, C++, SystemVerilog, MATLAB, Javascript, Intel Assembly, MIPS Assembly, Latex, Visual Basic. Service, Honors and Awards 1- IEEE Day Ambassador (2016-18), IEEE member (2017-Present), ACM member 2020-present 2- ... - Mar 23
... Languages: Verilog, TCL, VHDL, Python, C, C++, SystemVerilog, MATLAB, Javascript, Intel Assembly, MIPS Assembly, Latex, Visual Basic. Service, Honors and Awards 1- IEEE Day Ambassador (2016-18), IEEE member (2017-Present), ACM member 2020-present 2- ... - Mar 23
Design Engineer
Colorado Springs, CO
... solutions by collaboration with cross-functional teams and clients Competencies Digital ASIC/FPGA Design System Verilog, VHDL, Verilog HDL PCB Design and Verification Team Leadership & Mentoring Analog/Mixed-Signal Design Cross-functional ... - Mar 22
... solutions by collaboration with cross-functional teams and clients Competencies Digital ASIC/FPGA Design System Verilog, VHDL, Verilog HDL PCB Design and Verification Team Leadership & Mentoring Analog/Mixed-Signal Design Cross-functional ... - Mar 22
Power Electronics C++
Gainesville, FL
... Microprocessors & Microcontroller, Power Electronics TECHNICAL SKILLS Hardware Descriptive Languages & Methodology: System Verilog, Verilog, UVM, System Verilog Assertions, VHDL Programming & Scripting Languages: C/C++, Python, TCL, CUDA, MATLAB, ... - Mar 21
... Microprocessors & Microcontroller, Power Electronics TECHNICAL SKILLS Hardware Descriptive Languages & Methodology: System Verilog, Verilog, UVM, System Verilog Assertions, VHDL Programming & Scripting Languages: C/C++, Python, TCL, CUDA, MATLAB, ... - Mar 21
Junior studying computer engineering at Penn State
Eagleville, PA
... Anticipated Graduation: May 2026 ● GPA: 3.30/4.00 SKILLS Python Java Ignition SCADA software Studio 5000 Ladder Logic Assembly Verilog electrical design MS Power BI MS Power Automate blockchain WORK EXPERIENCE Johnson & Johnson Innovative Medicine ... - Mar 21
... Anticipated Graduation: May 2026 ● GPA: 3.30/4.00 SKILLS Python Java Ignition SCADA software Studio 5000 Ladder Logic Assembly Verilog electrical design MS Power BI MS Power Automate blockchain WORK EXPERIENCE Johnson & Johnson Innovative Medicine ... - Mar 21
Data Science, Machine Learning, design security, dynamic algorithms
Houston, TX
... in:Python, C, C++, Linux, Git, Anaconda, SQLite, MariaDB, TypeScript, Next.js, Java, React Native Familiar with:Rstudio, Verilog, Tensorflow, Scipy, JavaScript, Qiskit, MLxtends, SciKeras, Keras, Golang, OCR, Phoenix EXPERIENCE Full Stack App ... - Mar 21
... in:Python, C, C++, Linux, Git, Anaconda, SQLite, MariaDB, TypeScript, Next.js, Java, React Native Familiar with:Rstudio, Verilog, Tensorflow, Scipy, JavaScript, Qiskit, MLxtends, SciKeras, Keras, Golang, OCR, Phoenix EXPERIENCE Full Stack App ... - Mar 21
Design Verification Internship Opportunities
Washougal, WA
... RISC-V, MIPS Methodologies: UVM, Agile Protocols: I2C, Wishbone, UART, SPI Concepts: Data Structures, Digital Logic Design, System Verilog Assertions, Randomization and Constraints, Environment-based Verification, Coverage-Driven Verification, Code/ ... - Mar 20
... RISC-V, MIPS Methodologies: UVM, Agile Protocols: I2C, Wishbone, UART, SPI Concepts: Data Structures, Digital Logic Design, System Verilog Assertions, Randomization and Constraints, Environment-based Verification, Coverage-Driven Verification, Code/ ... - Mar 20
Electrical Engineering Student at RIT
Lancaster, NY
... Vim, Perl/Python, SystemVerilog/UVM, Synopsis, ModelSim, Lyx/LaTex, Ca- dence tools, Cirris Easy-Wire, TwinCAT 3, Banner Safety Software, TCP, CANopen, Verilog/VHDL, MATLAB, Assembly, SPICE, C/C++, Arduino IDE, Intel Quar- tus Prime, Ladder Logic. ... - Mar 16
... Vim, Perl/Python, SystemVerilog/UVM, Synopsis, ModelSim, Lyx/LaTex, Ca- dence tools, Cirris Easy-Wire, TwinCAT 3, Banner Safety Software, TCP, CANopen, Verilog/VHDL, MATLAB, Assembly, SPICE, C/C++, Arduino IDE, Intel Quar- tus Prime, Ladder Logic. ... - Mar 16
3rd Year Computer Engineering Student
Washington, DC
... Python, Svelte, C/C++, MATLAB, Java, Verilog Lab Tools: Oscilloscope, Soldering Iron, Multimeter, Digital Logic Analyzer, FPGA Digital Tools: Arduino, Autodesk Fusion 360, LINUX/UNIX, Git, VS Code, Xilinx Vivado, Eclipse Languages: French, Korean - Mar 15
... Python, Svelte, C/C++, MATLAB, Java, Verilog Lab Tools: Oscilloscope, Soldering Iron, Multimeter, Digital Logic Analyzer, FPGA Digital Tools: Arduino, Autodesk Fusion 360, LINUX/UNIX, Git, VS Code, Xilinx Vivado, Eclipse Languages: French, Korean - Mar 15
Data Analyst Analysis
Dallas, TX
... PROJECT EXPERIENCE Gained knowledge in Verilog and Completed project “Generating symmetric key by using Cryptography” with C language. Gained knowledge in Data Analytics and Engineering and completed project “A Data warehouse solution for Urban k ... - Mar 14
... PROJECT EXPERIENCE Gained knowledge in Verilog and Completed project “Generating symmetric key by using Cryptography” with C language. Gained knowledge in Data Analytics and Engineering and completed project “A Data warehouse solution for Urban k ... - Mar 14