Electrical Design Engineer with Controls & HW Expertise

LAKSHMI RANJEETHA ANEGUNDI

+1-773-***-**** *****************@*****.*** Apple Valley, CA, USA

PROFESSIONAL SUMMARY

Electrical Engineer with hands-on experience in electrical system design, industrial controls, and hardware development. Skilled in schematic and panel design using AutoCAD Electrical, PCB design, power electronics, and embedded control systems. Experienced with PLC-based control concepts, HMI/SCADA exposure, power distribution, and electrical system testing and commissioning support. Proficient in using oscilloscopes, logic analyzers, multimeters, and function generators for debugging and validation. Strong understanding of IEEE, NEC, IEC, and electrical safety standards, with the ability to support projects from design through field-ready implementation.

TECHNICAL SKILLS

• Electrical Design & Controls: Electrical system design, schematic and panel drawings, AutoCAD Electrical, wiring diagrams, BOM preparation, control systems fundamentals, PLC concepts (Allen-Bradley, Siemens), HMI/SCADA exposure, industrial automation concepts, power distribution, grounding, load flow and fault analysis

• Power Electronics & Hardware: DC-DC converters, buck converters, LDO regulators, analog and digital circuit design, multilayer PCB design and layout (Altium Designer, Eagle), power integrity, signal integrity, EMI/EMC mitigation, thermal management, ESD protection, board bring-up

• Semiconductor & VLSI – Hardware Design & Verification: Verilog HDL, SystemVerilog, UVM, OVM, C, Python, FPGA programming, ASIC development, VLSI design, static timing analysis, mixed-signal design, SoC integration, ModelSim, QuestaSim, Cadence Xcelium

• Testing, Debugging & Tools: Oscilloscopes, logic analyzers, multimeters, function generators, electrical measurements, waveform analysis, fault isolation, LTspice, PSpice, MATLAB/Simulink, ETAP, hardware validation, system troubleshooting, design verification

• Compliance & Standards: IEEE, IEC, NEC, NFPA 70E, ESD, LOTO, safety and quality protocols, design documentation

• Protocols & Embedded Systems: UART, I2C, SPI, AMBA (APB, AHB, AXI), embedded C, Python, C++, hardware–software integration and debugging

• Software & Soft Skills: Windows, Linux, MS Office, Git, Project Management, Problem-Solving, Critical Thinking EXPERIENCE

Electrical Engineer Horizon Semiconductor, USA Jan 2025 – Present

• Designed and optimized multilayer PCB layouts in Altium, reducing signal crosstalk by 15% and ensuring compliance with IPC and IEEE standards for high-speed electrical systems.

• Conducted power integrity & signal integrity simulations in LTspice and MATLAB, stabilizing voltage rails (3.3V/1.8V) with <5% ripple.

• Performed board bring-up, debugging, and validation of embedded hardware, resolving 25+ signal integrity issues and enabling seamless UART/SPI communication.

• Developed and calibrated mixed-signal circuits (ADC/DAC), achieving 95% accuracy across temperature and load variations.

• Created embedded test firmware in C for STM32 controllers to validate peripheral drivers (I2C, SPI, UART), supporting hardware–software integration.

• Collaborated with cross-functional design teams to ensure compliance with EMI/EMC, ESD, and thermal management requirements, improving system robustness.

Graduate Student Volunteer IEEE Computer Society Aug 2024 – Dec 2024

• Organized workshops on electrical engineering topics, including power electronics, circuit design, and SCADA systems, enhancing technical skills for 100+ participants. Collaborated with industry professionals to promote advancements in electrical systems, focusing on NFPA safety protocols and NEC compliance.

• Expanded professional network by connecting with experts in power systems, PLC programming, and HMI design. Digital Specialist Engineer Infosys, India Jun 2022 – Jul 2023

• Developed Python-based automation to analyze large-scale power and performance validation data, supporting engineering optimization.

• Built analytical dashboards correlating system parameters to reduce validation and QA cycles by 25%.

• Supported engineering teams with automated test analysis, improving system-level debugging and verification efficiency. Electrical Design and Verification Intern SOC-DV Pvt. Ltd, India Jun 2021 – Jul 2021

• Participated in the end-to-end PCB manufacturing process, from schematic design to final quality inspection.

• Designed and tested analog signal conditioning circuits for biomedical sensor applications, improving signal accuracy and reducing noise by 12%.

• Conducted DFM (Design for Manufacturing) and DFA (Design for Assembly) checks, ensuring manufacturability and reliability of printed circuit boards.

• Collaborated with engineers to perform functional and thermal testing of prototype boards, validating performance under variable load conditions.

• Assisted in preparing schematics, bill of materials (BOM), and wiring diagrams using Eagle CAD and AutoCAD Electrical. EDUCATION

Master of Science in Electrical and Computer Engineering University of Illinois at Chicago, Chicago, IL, USA May 2025

Relevant Coursework: Digital System Design, Computer Architecture, VLSI Design, Pattern Recognition, Quantum Bachelor of Engineering in Electronics and Communication Osmania University, Hyderabad, India June 2022

Relevant Coursework: Digital Electronics, Network Theory, Analog Circuits, Signal Processing PROJECTS

1x3 Router RTL Verification Verilog, MATLAB, Altium Designer Jan 2024 – Mar 2024

• Built UVM testbench (agent, sequencer, driver, monitor, scoreboard), achieving 98% coverage with SVAs.

• Optimized handshake protocols, reducing latency by 15% and ensuring AXI compliance. MAC Datapath for Neural Networks Cadence Virtuoso Sep 2023 – Nov 2023

• Designed optimized Verilog MAC with SRAM, boosting compute efficiency by 25%/

• Reduced power consumption by 15% and achieved timing closure at 800 MHz. Comparative Study of Adders Cadence Virtuoso Sep 2023 – Nov 2023

• Implemented and analyzed four adders in Cadence, automating PPA with Tcl.

• Identified Kogge-Stone’s 0.32 ns delay; selected carry-look-ahead for best speed/energy balance.

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