ASIC/RTL design engineer
Resume:
Sai Swetha
*************@*****.*** 955******* Hyderabad,India https://www.linkedin.com/in/a-sai-swetha/ SUMMARY
- Self-driven engineer with a Master's degree in Embedded Systems Engineering from NIT Jamshedpur, with nearly one-year of RTL design internship at Intel.
- Seeking opportunities to contributing expertise in ASIC,FPGA design and optimization in semiconductor solutions.
WORK EXPERIENCE
ONCHIP SPACE Semiconductors October 2025 - Present Project intern, RTL Design
- Designed and compiled combinational and sequential RTL modules following synthesizable coding guidelines and practices.
- Developed strong understanding of reset design methodologies,including proper usage of synchronous and asynchronous resets.
- Implemented RTL manual integration, including module instantiation, signal connectivity, and top-level design assembly and studied Magillem tool-based integration.
- Analysed RTL Synthesis tool flow
- Reviewed and documented RTL design practices,reset strategies,Lint,tool based commands, integration workflows and synthesis flow
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INTEL India Pvt Ltd Bangalore July 2022- May 2023 Intern, RTL Design Team
- Worked on server-class SoC RTL design hierarchy,understanding IP- subsystem – top-level SoC integration flow.
- Performed RTL static quality checks - Linting, clock/reset domain crossings as a part of pre- synthesis signoff.
- Utilized SpyGlass Static Analysis tools to debug violations, apply design constraints.
- Interpreted tool-generated reports and schematics to trace violations across RTL modules.
- Analysed multi-clock and reset structures to identify metastability risks and synchronization issues.
- Improved RTL quality by implementing CDC rule-based fixes reducing tool reported violations by 74%.
- Developed Perl automation scripts to parse SpyGlass logs and generate CSV-based violation summaries for design review and tracking.
- Gained hand-on exposure to industry RTL sign-off flows,including static checks,and coding best practices used in SoC integration.
KEY SKILLS
- Programming Languages: C Verilog System Verilog.
- EDA: RTL Simulation Synthesis and analysis(Synopsys Design Compiler, Fusion Compiler)
- Scripting: TCL, Perl.
- Core VLSI knowledge: RTL design, digital architecture, IP based design methodologies, timing concepts,
- Interfaces: AMBA(APB, AHB, AXI) SPI I2C UART.
- OS: Linux Windows.
- Tools and utilities: VC SpyGlass ModelSim EDA Playground Xilinx Vivado Microwind Git version control.
PROJECTS
- Static checks on server IP – Intel internship
- Conducted a thorough static verification of RTL designs to ensure early detection of errors reducing the risk of metastability and synchronization issues.
- Interpreted SpyGlass reports and schematics to trace violations across RTL modules.
- Achieved a 74% reduction in design violations,improving RTL quality and robustness.
- RTL Design, Integration and Synthesis Flow Project
- Designed and simulated basic logic gates,and other digital circuits including MUX, Counter,Clock dividers using verilog.
- Studied and applied synchronous and asynchronous reset methodologies.
- Performed manual RTL integration, and including hierarchical module instantiation and top-level connectivity.
- Reviewed and documented Magillem tool-based AHB Master-Slave integration.
- Analysed Synopsys Synthesis tool-flow, including automation script, commands and report analysis with technical documentation.
- Binary to Gray Code Converter using FPGA
- Developed a 4-bit Binary to Gray code converter using Verilog on an FPGA Spartan-3e, optimizing hardware resource utilization, reducing power consumption, and minimizing bit flip errors in high- speed digital communication.
CERTIFICATIONS
- Certification under ISWDP conducted by IISC,Bangalore in collaboration with Samsung and Synopsys for the participation and completion of level 1 on Semiconductor device technology and TCAD based 2D Device creation, simulation and analysis.
- Learning FPGA Development by LinkedIn Learning.
- MOOC (Massive Open Online Course) on VLSI Verification by NIELIT - Chips to Startup Programme (C2S), MeitY.
EDUCATION
- MTech – Embedded Systems Engineering
NIT Jamshedpur, 2023 CGPA: 8.19
- BTech – Electronics and Communication engineering SRITW, 2015 Grade: 76.54%
ADDITIONAL SKILLS
Critical thinking Problem-solving Team collaboration Continuous learning Listening Adaptability
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