Physical Design Intern - summer/Co-op Candidate, UT Austin

Hsiang Chin

+(1-737-***-**** ********@******.*** http://www.linkedin.com/in/hsiangchin

EDUCATION

• University of Texas at Austin Texas, USA

Master of Science in Electrical and Computer Engineering physical design Sep 2025 – Jun 2027

• National Central University Taoyuan, Taiwan

Bachelor of Science in Electrical Engineering, GPA 4.08/4.3, Top 7% Sep 2020 - Jun 2024 TECHNICAL SKILLS

• EDA and Design Tools: Xilinx Vivado, Virtuoso, Innovus, PrimeTime, Calibre DRC, LVS, VCS, HSPICE

• Programming Languages: Verilog, Python, C/C++, Matlab, Linux, OpenMP ICC2, Tempus, Quantus, VCS, Genus, Conformal, GDSll, Power, Area, Modeling, HDL, timing, CTS, APR, PnR, LEF, DEF, Layout, Schematic, Static timing analysis, DRC, LVS, Cadence, Synopsys, DFT, Tcl, Unix, VHDL, STA, clock trees, layout blocks, physical design, packaging, chiplet, CPU, computer architecture, timing reports, RISC-V, high performance, Perl, memory IP, Scripting, CAD tools, organizational skills, communication skills, project management, written and verbal communication skills WORK EXPERIENCE

• Micro- Ip Inc. Hsinchu, Taiwan

EDA Intern, Advanced Technology Development Team Jan 2024 - Aug 2024

Designed and research graph-based heuristics for spare TSV deployment in 3D ICs, jointly optimizing yield, and area overhead.

Participated in brainstorming and refining algorithmic ideas to improve robustness and solution quality.

• A Macro Placer for Minimizing Wire Length in Mixed-Size Design Flow EE Dept., NCU Research Assistant, Advisor: Professor Yu-Guang, Chen Jul 2022 - May 2023

Developed a macro placer with fine-tuning by flipping macro-orientations and centralizing routing resources, achieving up to a 16.6% reduction in computation time.

Utilized a self-defined "Discriminant Equation" to gather winding resources and facilitated standard- cell placement, achieving up to a 7.2% reduction in HPWL.

• Optimizing Floorplanning with Soft-Module Configuration in Fixed-Outline Designs EE Dept., NCU Research Assistant, Advisor: Professor Yu-Guang, Chen May 2023 - Dec 2023

Optimized HPWL (Half-Perimeter Wire Length) by fine-tuning soft module placement through 64 combinations of aspect ratios and movement directions.

Utilized "deformation" techniques to identify module contour, thereby reducing wasted space within the chip and reshaping soft modules, achieving a notable 33.34% reduction in HPWL. SELECTED PROJECTS

• Design of Arithmetic Logic Unit with Four Functional Blocks ECE Dept., UT Austin Advisor: Professor David Pan Sep 2025

Designed and implemented logic, comparison, arithmetic, and shift operations using gate-level circuits.

Performed layout APR using Innovus and conducted pre- and post-layout timing analysis with PrimeTime.

• 20 nm CMOS Inverter & SRAM Sub-Array Characterization for Timing Modeling ECE Dept., UT Austin Advisor: Professor David Pan Oct 2025

Characterized a 20 nm CMOS inverter in Cadence/HSPICE across input-slew and output-load corners, extracting Tr/Tf to build delay-vs-slew/load data for timing-library modeling.

Designed a latch-based 4-bit memory cell and 32 32 SRAM array model in Virtuoso/Spectre, including P/G rail planning, RC bitline/wordline delay modeling, and worst-case read-access time analysis.

• ARM2 SoC with SSP – RTL-to-Layout Physical Implementation in 45 nm ECE Dept., UT Austin Advisor: Professor David Pan Nov 2025

Implemented a synthesizable Synchronous Serial Port (SSP) in Verilog and drove synthesis in Design Vision as input to back-end APR.

Integrated ARM2, instruction memory, and SSP via WISHBONE and clock-management logic, then completed 45 nm full-chip APR and post-layout timing checks in Cadence Innovus. SELECTED COURSES

• Graduate-Level: CAD for VLSI Design, Memory Circuit Design, VLSI Design, Hardware and Software Codesign, Multithreaded Architecture Programming and Tools

• Undergraduate-Level: Digital System Design and Implementation, Digital Logic Circuit Laboratory, Signals and Systems, Computer Organization, Special Project on VLSI Design, Electronic Circuits Lab.

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