Entry-Level Design Verification Engineer (UVM/SystemVerilog)

Rashmi R

Bengaluru +91-636******* ************@*****.***

Profile Summary

Design Verification Engineer skilled in SystemVerilog, UVM, and AMBA APB protocol verification. Completed 6-month training at ChipEdge Technologies, Bengaluru. Experienced in building UVM testbenches, developing drivers, monitors, and scoreboards, and performing coverage and assertion-based verification using Synopsys VCS and Linux tools. Enthusiastic about creating efficient and reusable verification environments for complex SoC designs. Education

M.Tech in VLSI Design and Embedded Systems, Dr. Ambedkar Institute of Technology, Bengaluru-2024

B.E. in Electrical and Electronics Engineering, Sri Venkateshwara College of Engineering – 2022

Professional Training

Completed 6-month Design Verification course at ChipEdge Technologies Pvt. Ltd., Bengaluru (Jan 2024 – Aug 2024), covering SystemVerilog, UVM, and AMBA protocols using Synopsys VCS.

Technical Skills

Verification Languages: SystemVerilog, Verilog

Methodology: UVM

Protocols: AMBA APB

Tools: Synopsys VCS, EDA tools

Operating Systems: Linux, Windows

Projects

• Verified APB Slave DUT using APB Master Testbench in SystemVerilog.

- Developed APB Master Testbench operating at 100–250 MHz.

- Designed Driver, Monitor, Scoreboard, and functional coverage.

- Created directed and random testcases for data, address, and error handling.

- Verified DUT functionality and protocol compliance under varied clock conditions.

• Developed UVM-based Testbench for APB Master (V4.0).

- Built complete UVM environment with virtual interface connections.

- Implemented Driver, Monitor, Scoreboard, and Sequences for write/read operations.

- Added coverage and assertions to ensure thorough verification.

- Experienced in UVM phases, factory, and configuration database usage. Preferred Job Locations

Bengaluru Hyderabad Chennai

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