Electronics Engineering Student Seeking Internship in Microelectronics

LE VIET HOANG

District **, Ho Chi Minh City, Vietnam

+84-035-***-**** ***************@*****.*** github.com/viethoang2k3fov youtube.com/@hoangleviet9507 EDUCATION

Bachelor of Engineering in Electronics and Telecommunications September 2021 – December 2025 Ho Chi Minh City University of Technology (HCMUT), Vietnam TOEIC : 620

SKILLS

Programming Languages Verilog HDL, SystemVerilog, C, SystemC Design / Simulation Tools Cadence Virtuoso, ModelSim, Quartus, QuestaSim Operating Systems & Editors Linux, Vim Editor, Shell Scripting (Bash) KNOWLEDGE

RTL Design Verilog HDL, FSM (Moore/Mealy), FIFO, Registers, MUX Design Verification SystemVerilog, Functional coverage, Debugging, Basic UVM Communication Protocols I2C, UART/USART, SPI, AXI, APB, AHB Digital IC Design Combinational / Sequential Logic, CMOS, Elmore Delay, Power, Layout PROJECTS

FPGA-Based Automatic Fuel Measurement and Pumping System September 2025 – December 2025 Graduation Project Score: 9.0 / 10

· Designed and implemented an automatic fuel pumping system based on FPGA platform

· Developed RTL modules using Verilog, including control logic, finite state machines (FSM), and sensor interfacing

· Integrated ultrasonic sensors for fuel level measurement and implemented real-time monitoring

· Verified system functionality through simulation and on-board testing Design and Implementation of an FPGA-Based Digital Clock March 2025 – June 2025 Major Project Score: 9.0 / 10

· Designed and implemented a digital clock system on FPGA platform

· Developed Verilog RTL modules for time counting, clock division, and control logic

· Implemented finite state machines (FSM) for mode control and time adjustment

· Verified functionality through simulation and on-board testing Design and Analysis of an 8-Bit SRAM Memory February 2024 – May 2024 Major Project Score: 8.5 / 10

· Designed and analyzed an 8-bit Static Random-Access Memory (SRAM) at circuit level

· Implemented basic SRAM architecture including memory cells, wordlines, and bitlines

· Analyzed read and write operations to verify correct memory functionality

· Evaluated memory behavior through simulation and waveform analysis Design and Analysis of an FPGA-Based Waveform Display System February 2025 – May 2025 Course Project Score: 9.0 / 10

· Designed and implemented a multi-waveform signal generator on FPGA platform

· Generated various waveforms including Sine, Square, Triangle, Sawtooth, and ECG signals

· Developed Verilog RTL modules for waveform synthesis and signal switching

· Verified waveform accuracy through simulation and hardware testing

Contact this candidate