Hardware Product Engineer - NPI & Validation Specialist

HEMANTH BARAGURU SRINIVASA MURTHY

Irvine, CA 984-***-**** ***************@*****.*** www.linkedin.com/in/hemanthbaraguru PROFILE SUMMARY

Innovative and results-driven Product Engineer with 2 years of experience in New Product Introduction (NPI), hardware validation, PCB/hardware design, and supply chain/component engineering. Proven ability to lead cross-functional initiatives from concept to production, ensuring high reliability, cost efficiency, and manufacturability. Skilled in Altium Designer, OrCAD, Cadence Allegro, LTspice, LabVIEW, NI TestStand, and hands-on with oscilloscopes, logic/network analyzers, and other test equipment. Adept in BOM management, component selection, supplier sourcing, and driving DFM/DFA improvements within Agile and Six Sigma environments. Strong knowledge of IPC standards, RoHS/REACH compliance, and PLM tools like Arena and Windchill, with a passion for delivering robust and scalable hardware solutions across industrial, automotive, and consumer electronics sectors. EDUCATION

North Carolina State University May 2025

Master of Science, Computer Engineering (GPA: 3.81/4.0) Coursework: ASIC and FPGA Design with Verilog, ASIC Verification, Advanced Functional Verification with UVM, Cryptographic Engineering and Security, Microprocessor Architecture, Advanced Computer Architecture, Architecture of Parallel Computers. Bangalore Institute of Technology May 2023

Bachelors of Electronics and Communication Engineering (GPA: 3.54/4.0) TECHNICAL SKILLS

• Hardware Design & Validation: Altium Designer, OrCAD, Cadence Allegro, LTspice, LabVIEW, NI TestStand, oscilloscopes, logic/network analyzers, PCB stack-up planning, impedance control, thermal management, schematic capture, multilayer PCB layout, SMT assembly, signal integrity analysis, qualification testing, functional testing, hardware debug, DFM/DFA optimization.

• Product Lifecycle & Supply Chain Management: Agile PLM, Arena PLM, Windchill, ERP systems, CMRP, BOM management, vendor coordination, component selection, procurement, supplier sourcing, SharePoint documentation, NPI process, production planning, manufacturing yield optimization, cost reduction strategies.

• ASIC/FPGA & Verification: Verilog, SystemVerilog, UVM, UVM Framework (UVMF), constrained random verification, assertion-based verification, ModelSim, Xilinx Vivado, RTL design, functional verification, testbench creation, timing analysis, post-quantum cryptographic hardware design, FPGA prototyping, simulation, and synthesis.

• Programming & Simulation: C++, MATLAB, Python, cache/memory hierarchy simulation, processor simulation, dynamic branch predictor modeling, algorithm optimization.

• Standards & Compliance: IPC standards, RoHS/REACH compliance, Six Sigma methodology, ISO standards, quality control, regulatory compliance, design for reliability, manufacturability, and assembly (DFM/DFA).

• Soft Skills & Leadership: Cross-functional collaboration, problem-solving, root cause analysis, project coordination, documentation, mentoring/junior guidance, time management, effective communication.

• Domains & Applications: Industrial electronics, consumer electronics, automotive hardware, cryptographic engineering, embedded systems, FPGA/ASIC design, computer architecture, quantum computing emulation, high-speed PCB design, multi-chip module integration.

PROFESSIONAL EXPERIENCE

Product Engineer Trainee, Hummingbird TekSystems Inc May 2025 - Present

• Contribute to hardware board design by updating schematics and implementing PCB layout modifications to support new features and improve overall design.

• Develop and maintain detailed test procedures and documentation to ensure repeatability and compliance with engineering standards.

• Perform comprehensive board-level hardware testing, including both functional and qualification (Qual) testing, while identifying issues and supporting root cause analysis.

• Procurement of electrical components required for product development and coordinated with vendors to ensure timely delivery and expedition of materials.

NPI Intern, Skyworks Solutions Inc Jan 2025 - May 2025

• Validated 50+ unique printed circuit board (PCB) designs against electrical and manufacturing constraints using Allegro PCB Designer, generating comprehensive Bill of Materials (BOMs), reducing potential production errors, and expediting time to market.

• Implemented Design for Manufacturability (DFM) principles in PCB designs, decreasing manufacturing defects by 12% and slashing rework costs within the new product introduction cycle.

• Categorized three generations of Engineering Validation Boards (EVB) using laser via structures, pad sizes, pitch spacing, and material stack-up for optimized component sourcing, decreasing supplier lead times by 15%.

• Prepared and released complete PCB documentation packages—including Gerbers, ODB++, and assembly drawings—into Agile PLM; enabled seamless handoff to manufacturing and reduced fabrication delays.

• Executed Design Rule Checks (DRC) and addressed Engineering Queries (EQs) concerning PCB stack-up, layer-to-layer registration, drilling methodologies, array configurations, tolerance specifications, and pad size variations; accelerated procurement cycles by 7 days through proactive issue resolution and strengthened cross-functional collaboration.

• Orchestrated the procurement of 150+ Engineering Validation Boards (EVB), Automated Test Equipment (ATE) boards, and Multi- Chip Module (MCM) boards for NPI projects, ensuring timely availability and zero downtime in production cycles.

• Leveraged Enterprise Resource Planning (ERP) systems to create weekly build plans, decreasing excess component inventory and minimizing production delays by 10%.

• Revamped the existing vendor documentation system utilizing SharePoint, reducing the time spent searching for critical component specifications, and compliance information.

• Managed and analyzed the CMRP (Capacity Material Requirements Planning) report to streamline warehouse operations, optimize storage utilization, and reduce inventory-related delays by 25%. Layout Design Intern, Bharat Electronics Limited Aug 2022 - Feb 2023

• Demonstrated adept utilization of Cadence software, showcasing advanced proficiency in Integrated Circuit design and fabrication methodologies.

• Acquired comprehensive expertise in the design, development, and manufacturing of electronic hardware systems, including schematic design, PCB design, multilayer PCB layout, Surface Mount Technology (SMT), and end-to-end hardware development—from component selection and signal integrity analysis to testing and validation.

• Led the full lifecycle of hardware design, including PCB stack-up planning, impedance control, thermal management, and Design for Manufacturability (DFM) considerations, ensuring optimal performance and production efficiency.

• Forged alliances between design engineers and authorized vendors, reducing design review cycles by 20% and enabling faster iterations and prototyping of custom PCB designs. PROJECT EXPERIENCE

Quantum Computing Emulator Verilog - ASIC Design

• Developed a quantum computing emulator, implementing complex values for up to 4 Qubits and utilizing SRAM interface.

• Engineered critical path improvements to achieve a 26ns clock period, ranking in the top 15% out of 213 projects.

• Validated the design by passing all test cases in ModelSim, confirming 100% functional accuracy and stability. R-BinLWE Based 256-bit Post-Quantum Decryption Verilog – Cryptographic Engineering and Hardware Security

• Implemented R-BinLWE decryption data path in Verilog for 256-bit inputs with degree-256 polynomial and modulo256 arithmetic.

• Developed ring-based modular addition, multiplication, and threshold decoding modules for secure post-quantum processing.

• Verified full functional correctness using a 5-vector testbench, ensuring 100% match with expected outputs across all simulations.

• Synthesized and optimized using Xilinx Vivado 2024.1 on Spartan-6 FPGA, achieving ~256 clock cycles per decryption. Verification of I2C Multi Bus Controller System Verilog - ASIC Verification

• Designed and analyzed a reusable, scalable I2CMB verification environment using layered test bench.

• Engineered complete verification suite for I2C Multi Bus Controller using System Verilog, achieving 99% functional coverage through constrained random verification and assertion-based methodologies, surpassing target metrics. LC3 Verification using UVM System Verilog - Advanced Functional Verification with UVM

• Created a UVM verification environment for the LC3 decode stage, including the interface packages and functional coverage based on the LC3 specification.

• Leveraged UVM Framework (UVMF) to modularize and extend the verification environment across all pipeline stages, enabling scalable testbench development and achieving 100% functional coverage. Cache Design, Memory Hierarchy Design C++ - Computer Architecture

• Developed a cache simulator featuring Write-Back Write-Allocate (WBWA) and Least Recently Used (LRU) replacement policies; the simulator reduced memory access latency by 15% under heavy workloads, as verified through testing.

• Evaluated performance with varied cache configurations, offering diminishing reduction in miss rates.

• Integration of a stream buffer pre-fetcher with the L1 or L2 cache resulted in 10% reduction in miss rate. Out-of-Order (OOO) Superscalar Processor Simulator C++ - Computer Architecture

• Simulated a 9-stage pipeline for Out-of-Order (OOO) execution capable of executing N instructions per cycle with dynamic scheduling.

• Implemented a Rename Map Table (RMT), Re-Order Buffer (ROB) to facilitate hazard free OOO execution. Dynamic Branch Predictor Simulator C++ - Computer Architecture

• Simulated dynamic branch prediction in a microprocessor.

• Modelled and compared the performance for a bimodal, gshare and hybrid branch predictor by analyzing the miss- prediction rates. The gshare predictor outperformed, yielding a 6.3% miss-prediction rate.

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