| Distance: | Resume alert | Resumes 391 - 400 of 5927 |
Software Engineering Electrical
Fremont, CA
... CD, Ansible Data: ETL, Hadoop, Spark, Tableau Testing: Selenium Blockchain: Ethereum, NFT, Web3, Smart Contract Hardware: Verilog, RTL, Chip Design, Chiplet, EDA, Firmware, CUDA, UVM Leadership: Agile, SCRUM Compliance: PCI, HIPAA CERTIFICATE Azure ... - 2023 Nov 18
... CD, Ansible Data: ETL, Hadoop, Spark, Tableau Testing: Selenium Blockchain: Ethereum, NFT, Web3, Smart Contract Hardware: Verilog, RTL, Chip Design, Chiplet, EDA, Firmware, CUDA, UVM Leadership: Agile, SCRUM Compliance: PCI, HIPAA CERTIFICATE Azure ... - 2023 Nov 18
Verilog, Python, C/C++
Phoenix, AZ, 85003
... Visvesvaraya Technological University Belgaum, India Aug 2017 – Aug 2021 Bachelor of Engineering, Electronics and Communication Engineering GPA 3.8/4 Coursework- VLSI Design, Digital Electronics, Analog Electronics, Verilog and VHDL, Microprocessors ... - 2023 Nov 17
... Visvesvaraya Technological University Belgaum, India Aug 2017 – Aug 2021 Bachelor of Engineering, Electronics and Communication Engineering GPA 3.8/4 Coursework- VLSI Design, Digital Electronics, Analog Electronics, Verilog and VHDL, Microprocessors ... - 2023 Nov 17
C C++ Embedded Systems
Quan 1, 710000, Vietnam
... READING COMPREHENSION C/C++ DESIGN DIGITAL CIRCUIT BASIC VERILOG UNIVERSITY OF INFOMATION TECHNOLOGY - VIET NAM NATIONAL UNIVERSITY HO CHI MINH CITY GPA: 6.54 Subjects Learned: introduction to embedded-system programming, embedded systems, embedded ... - 2023 Nov 16
... READING COMPREHENSION C/C++ DESIGN DIGITAL CIRCUIT BASIC VERILOG UNIVERSITY OF INFOMATION TECHNOLOGY - VIET NAM NATIONAL UNIVERSITY HO CHI MINH CITY GPA: 6.54 Subjects Learned: introduction to embedded-system programming, embedded systems, embedded ... - 2023 Nov 16
Software Engineer Senior Manager
Highlands Ranch, CO
... BSCAD created BS-verification test platform, test vectors, BS-logic in VHDL & Verilog for gate-level simulation. • Maintained code in SABLIME version control system for bug resolution. • Created a web-based form for generating 16-bit ID for the ... - 2023 Nov 15
... BSCAD created BS-verification test platform, test vectors, BS-logic in VHDL & Verilog for gate-level simulation. • Maintained code in SABLIME version control system for bug resolution. • Created a web-based form for generating 16-bit ID for the ... - 2023 Nov 15
Entry Level Fpga Design
New Delhi, Delhi, India
... AREAS OF EXPERTISE Software Proficiency: EDA Tools : ModelSim, Mentor Graphics Tool, OrCAD, Operating System : Windows Family Vlsi Programming Language : Verilog HDL Programming Tool : Xilinx ISE Design Suite 14.5, Designing Tool : ORCAD, Proteus ... - 2023 Nov 08
... AREAS OF EXPERTISE Software Proficiency: EDA Tools : ModelSim, Mentor Graphics Tool, OrCAD, Operating System : Windows Family Vlsi Programming Language : Verilog HDL Programming Tool : Xilinx ISE Design Suite 14.5, Designing Tool : ORCAD, Proteus ... - 2023 Nov 08
Ic Design Engineer
Portland, OR
... feedback technique for 1/f flicker noise up-conversion suppression in SiGe:C BiCMOS process Skills CAD tools: MATLAB, Verilog/VerilogA, Synopsys Hspice, Cadence tools (Spectre, ADE/Virtuoso XL), Cadence EMX, Agilent ADS/Momentum/FEM, Ansys HFSS, ... - 2023 Nov 07
... feedback technique for 1/f flicker noise up-conversion suppression in SiGe:C BiCMOS process Skills CAD tools: MATLAB, Verilog/VerilogA, Synopsys Hspice, Cadence tools (Spectre, ADE/Virtuoso XL), Cadence EMX, Agilent ADS/Momentum/FEM, Ansys HFSS, ... - 2023 Nov 07
Sql Server Software Development
Plano, TX
... Programming Languages: T-SQL,Oracle SQL, PL/SQL, PostgreSQL, Kafka, MongoDB, java, C++, C#, VHDL, Verilog, FPGA Cloud Technologies: AWS, Microsoft Azure, Snowflake. Ticketing Applications: JIRA, Service now. Microsoft Office: MS Word, MS Excel, MS ... - 2023 Nov 01
... Programming Languages: T-SQL,Oracle SQL, PL/SQL, PostgreSQL, Kafka, MongoDB, java, C++, C#, VHDL, Verilog, FPGA Cloud Technologies: AWS, Microsoft Azure, Snowflake. Ticketing Applications: JIRA, Service now. Microsoft Office: MS Word, MS Excel, MS ... - 2023 Nov 01
Design Engineer Rtl
San Jose, CA, 95118
... channeled low-power DMA for controllers Verified DDR3 interface using System Verilog (VMM), Designed DSP blocks (FIR/IIR, FFT) Designed High Speed Serial Link (6 GHz) using 65nM technology (IBM) Designed CACHE controller (MESI and MOESI) for MPU. ... - 2023 Oct 31
... channeled low-power DMA for controllers Verified DDR3 interface using System Verilog (VMM), Designed DSP blocks (FIR/IIR, FFT) Designed High Speed Serial Link (6 GHz) using 65nM technology (IBM) Designed CACHE controller (MESI and MOESI) for MPU. ... - 2023 Oct 31
Design Engineer Electrical
Greensboro, NC
... (Nov/2022-PRESENT) Skills Altium Designer MATLAB OrCAD AutoCAD Allegro Six Sigma Black Belt Proteus Six Sigma Green Belt PIC C compiler Six Sigma Yellow Belt C++ C Programming for Embedded Applications Python LabVIEW C# IPC-A-610 FPGA VHDL, Verilog ... - 2023 Oct 31
... (Nov/2022-PRESENT) Skills Altium Designer MATLAB OrCAD AutoCAD Allegro Six Sigma Black Belt Proteus Six Sigma Green Belt PIC C compiler Six Sigma Yellow Belt C++ C Programming for Embedded Applications Python LabVIEW C# IPC-A-610 FPGA VHDL, Verilog ... - 2023 Oct 31
IT technician
Lubbock, TX
... Programming Languages: Python, HTML, Java, C, Verilog, Assemble language. General Programs: Microsoft Office (Word, Excel, PowerPoint) Languages: English, French, basic Spanish. Skills: OOP, Data structures, Algorithms,Operating systems, Computer ... - 2023 Oct 28
... Programming Languages: Python, HTML, Java, C, Verilog, Assemble language. General Programs: Microsoft Office (Word, Excel, PowerPoint) Languages: English, French, basic Spanish. Skills: OOP, Data structures, Algorithms,Operating systems, Computer ... - 2023 Oct 28