Sandipan Basu
Email ID: ********.****@*****.***
919-***-**** (Cell)
Summary
Expertise in Microprocessor (CPU) Verification, Pre-& Post Silicon CPU & SOCs Verification, Embedded System Development, HW bring-up, requirements Gathering, Multi-core Systems Engineering, Planning, Designing, Network protocol stack design & development, and Coding using C, C++, IXP1200 Microcode, Micro-Engine C, Assembly language (Lucent DSP), System Verilog, scripting language.
Experience
Verify architecture and micro-architecture functionality and performance for ARM Level-2 cache micro-architecture functionality, Cache coherency protocol, internal pipeline with multi-core CPUs
Embedded System Software design, development and incorporating in a large project
Display Controller, HDMI device driver, ATM SAR Device drivers
Unified Extensible Firmware Interface (UEFI)
Strong architecture knowledge of PowerPC MPC 860, PowerPC 8260, Network processor IXP 1200, Lucent DSP 1650, ARM.
Serial communication protocol, Device Driver Development, RISC Processor architecture, Digital Signal Processing (DSP)
Network stack (Frame Relay) Design and development, SONET APS (Asynchronous protection Switch) for OC3 line, ATM, Ethernet, PCIe, TCP, UDP, IP, DHCP Snooping.
Technical Skills
Operating Systems: RTOS (VxWorks), Linux, QNX
Languages & Other Software: C, C++, Assembly Language, Verilog, System Verilog, UVM, UNIX Shell, Perl, Python
Version Controls: CVS, Clear Case, CMVC
Achievement
Outstanding Achievement Award from Qualcomm
Employee Recognition award by Research in Motion
Best Engineer award for Alcatel project
Professional Experience
Itron 02/23 – till
Senior Firmware Engineer
Project: Metering system
Environment: C, C++
Description: Implement new features and Upgrade existing metering firmware code
Role in the project:
Implement new features in different Metering devices.
Debug and improve existing codes.
IBM 05/22 – 02/23
Verification Engineer
Project: Verification on IBM chips.
Environment: C++, Perl
Description: Design verification CPU Array of Register logic
Role in the project:
Functional verification to work on IBM chips
Debugging Waveforms, log files, trace logs
Develop test code and fix simulation environment files.
ACL Limited 12/20 – 04/22
Design Verification Engineer
Project: RISC-V microarchitecture verification
Environment: C, C++, RISC-V Assembly
Description: Design verification CPU LSU logic
Role in the project:
Microprocessor architecture and pipelining technique to verify the following logic:
Develop testplan for LSU
Microlevel verification for LSU pipeline, different LSU instructions, L1 & L2 Cache, DTLBs, exceptions.
Test, and debug fail scenarios.
IBM 06/18 – 11/20
uEFI Firmware Engineer
Project: uEFI (Unified Extensible Firmware Interface), OpenStack
Environment: C, C++, Peripheral Devices (e.g. PCIe, HPET, iSCSI…), Linux, Python
Description: Improve, debug, and fix uEFI firmware. Part-time support OpenStack for PowerPC,
Role in the project:
Improve, debug, and fix uEFI firmware logic
Test, debug and fix OpenStack CI for KVM on PowerPC
Qualcomm 07/16 – 06/18
Design Verification Engineers for Coherent Bus Verification
Project: SOC Coherency Bus Verification
Environment: C, C++, UVM, System Verilog, Perl
Description: Develop transactors for bus protocols, and design verification for several high-speed configurable bus designs.
Role in the project:
Write random tests to verify bus Coherency algorithm, L3 cache.
Develop verification environments, verification of complex designs until coverage goals are achieved dynamically or statically, and completing all required verification activities at IP
Test, and debug fail scenarios.
IBM 10/14 – 07/16
uEFI Firmware Engineer
Project: uEFI (Unified Extensible Firmware Interface), OpenStack
Environment: C, Peripheral Devices (e.g. PCIe, HPET, iSCSI…), Linux, Python
Description: Improve, debug, and fix uEFI firmware. Part-time support OpenStack for PowerPC,
Role in the project:
Improve, debug, and fix uEFI firmware logic
Test, debug and fix OpenStack CI for KVM on PowerPC
Design and develop ConnectX chip hard reset logic, and also reset from PCIe upstream link; restore RDMA protocol.
Improve, debug and fix Interconnect related issues.
NetApp 11/12 – 10/14
Software Engineer
Project: High Availability Interconnect protocol
Environment: C, PCIe bus, ConnectX IB (InfiniBand) network protocol chip.
Description: Improve the existing RDMA protocol, implement ConnectX chip reset logic.
Role in the project:
Design and develop ConnectX chip hard reset logic, and also reset from PCIe upstream link; restore RDMA protocol.
Improve, debug and fix Interconnect and Platform related issues.
Research In Motion 10/10 - 10/12
Platform Engineer
Project: Next Generation Platform Firmware Development & Verification (Board bringup)
Environment: C, C++, ARM assembly Language, QNX RTOS, Microprocessor architecture, Uboot, HW bring-up, TI & Marvell processor architecture, Cache Coherency protocol.
Description: To create early-stage software to Enable Better RIM Handheld Devices.
Role in the project:
Microprocessor architecture and pipelining technique to design, coding and verify the following logic:
Design and develop next generation device drivers like Display Controller, HDMI, UniPro.
Involved in debugging, designing, coding, testing and implementation of software modules.
Make OS independent layer to support Linux and Qnx Operating System.
Develop MESI cache coherency protocol.
Experienced with Momentics debugger for debugging.
Qualcomm 06/06 – 09/10
Verification Engineer
Project: Scorpion UNI and Multi core CPU
Environment: C, Verilog, System Verilog, Perl, Unix Shell, ARM assembly Language, Microprocessor architecture and pipeline, L2 Cache and pipeline, Debussy debugger.
Description: Scorpion is a high-performance implementation of the ARMv7 architecture.
Role in the project:
Microprocessor architecture and pipelining technique to verify the following logic:
L2 Cache pipeline, Cache Coherency
AXI bus, Slave Port, Tightly Coupled Memory (TCM), Direct Memory Access (DMA)
CPU registers with different securities and different processor mode.
Alcatel 06/02 - 05/06
Sr. Embedded System Software Engineer
Project: Fiber To The User (FTTU), FASTPATH Networking Software, Container Service Gateway
Environment: C, C++, PowerPC 8260, RTOS (VxWorks), Broadcom BCM5690 & BCM56504-XGS3, C, Intel IXP1200 Assembly Language, IXP micro-engine RTOS (VxWorks).
Description: Fiber to the User (FTTU) solution delivers the next generation of broadband services with an all-optical access.
Role in the project:
Design and develop Driver code for the following-
oATM SAR and I2C on MPC8260 FCC controller
oHCL bus Termination Interface Module on FPGA.
oUART (RS-232)
oSPI (Serial Peripheral Interface), I2C
oHDLC (High-level Data Link Controller) protocols for T1 Line (DS0)
oDallas DS1994 RTC, Music On Hold Chip (PSB 2163)
Write, debug Bring-up board; download code; communicate with workbench and integrate device drivers.
Design, develop device driver & enhanced Ethernet network protocol e.g. DHCP Snooping,, Spanning Tree protocol (SPT), Port Naming, BPDU Filtering, Port Mirroring, PHY Diag on Broadcom network peripheral chips, CLI.
Involved in code develop, Bug fixing, code reviews.
Debug BSP initialization code; customize the BSP makefile, download code, U-Boot
Design, develop & modify network protocol for- TCP/IP, HTTP on IXP1200 processor
Experienced with serial and Vision Click JTAG debugger for debugging.
Used IXP workbench simulator debug tool for debugging
BSP support
Designed and Developed Frame relay stack on IXP 1200 processor based Orchestra system- Data and Control Path.