LE TRUONG VY
Veri cation Engineer
079******* ad3ahz@r.postjobfree.com https://www.facebook.com/pro le.php?id=100************ Disctrict 10, Ho Chi Minh city
To seek and maintain full-time position that offers professional challenges utilizing interpersonal skills, time management and problem- solving skills.
TARGET
EDUCATION
HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY 09/2017 - 04/2022 Electronics - Telecomunications Engineering
EXPERICENCE
RENESAS DESIGN VIETNAM CO, LTD 03/2022 - 05/2023
Engineer
- Preparing and maintaining of speci c documents and data like functional speci cations.
- Understand micro-architecture of the block to be veri ed, and develop and execute test plans for the same.
- Knowing about verifying design at block level and system level using constraint random environment.
- Have knowledge about Verilog Assertions, Code/functional coverage.
- Using simulation tools, debug tools to debug functional errors in RTL models. SKILL
Simulates Tools: Design Compiler, VCS,Verdi,Jasper Gold, Model Sim, Quartus. Scripting languages: Perl, Shell and Python.
Formal veri cation: Working experience with Jasper Gold or similar. Veri cation: Knowledge of Verilog and basic knowledge of System Verilog for veri cation English: Quiet good communication and written skills in English. PROJECTS
Thesis Project:
VERILOG IMPLEMENTATION OF RSA CRYPTOGRAPHY ALGORITHM // 10-2020 - 08-2021 Description:
Designed two modules use to protect the message when it is sent to receiver, one is encode the message and send to receiver, and the other one is decode to get the message. Using Verilog to build module, and simulate tools like Model sim and Quartus to check the module. Project:
MCU RH850/U2x // 05-2022 - 04-2023
Description:
-Modi ed spec design module based on checking customer requirement as SRD/PRD.
-Veri ed all patterns of module to con rm all required fuctions of chip.
-Used functional coverage to con rm the design's functionality has been covered by tests.
-Made patterns description for each module veri ed.
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