Circuit Design Mixed Signal

KHUDSIYA TAJ

College Station, TX Phone: +1-979-***-****; Email id: ***********@*****.***

EDUCATION:

Texas A&M University, College Station, TX Aug 2022 – May 2024 Master of Science in Electrical Engineering (Analog and Mixed signal circuit design) GPA: 3.89/4.00 Coursework: Analog VLSI Circuit Design, PLL and CDR design, Advanced Analog circuit design, Low noise electronics, Digital VLSI Circuit design, Microprocessor design, Mixed Signal interfaces, Wireless Communications R.V College of Engineering, Bangalore, India Aug 2015 - June2019 Bachelor of Engineering in Electronics and Communications Engineering GPA: 8.54/10.00 Coursework: Analog Integrated Circuit design, RFIC, DSP, Analog/Mixed Mode VLSI Design, VHDL and Verilog Digital design, Digital VLSI design, Wireless Communications

SKILLS:

Design tools & Programming: Cadence Virtuoso Schematic, maestro, Spectre, ADE, ADE L, Layout XL, PVS, Calibre, Xilinx Vivado, Linux OS, C, C++, Python, Verilog, MATLAB (Programming & Simulink), LabVIEW EXPERIENCE:

Texas A & M University, College Station, TX Aug 2023-Dec 2023 Student Worker under Dr. Jose Silva Martinez

• Analysis of Camera Module integration with FPGA helping his PHD students in test and characterization. Allegro Microsystems, Manchester, New Hampshire May 2023-Aug 2023 Analog Design Engineering Intern – Current Sensor Group

• Redesign and Comparison study of npn based and cmos based bandgaps.

• Reducing the mismatch of current mirror which was used in above bandgaps.

• In package SCAN test setup using ASEK 20.

National Instruments, Bangalore, India Aug 2019 – June 2022 RF staff software engineer- RFmx WLAN DSP algorithm test and development

• Test development and execution of the WLAN measurements on NI PXIe 5840/41, 5831/30 under different configurations.

• Experience in WLAN 802.11 n,ac,ax and be standards.

• Design and implementation of physical layer signals for WLAN

• Verification and validation lead of WLAN DSP algorithm team for 6 months and had complete responsibility of test plan, test infrastructure update, test execution and collaborate with software team for end-to-end testing for multiple parallel projects. Jiva Sciences Pvt. Ltd Bangalore, India Jan 2019 – May 2019 Electronics Engineering Intern

• Implemented Analog front end module for highly sensitive laser-based cell detecting system.

• Comparison study and implementation of DAQ systems. ACADEMIC PROJECTS:

Design of 3 stage 1.6V LDO Jan 2023-May 2023

• Design of a 2-stage miller compensated op-amp which is used as an error amplifier.

• Design of differentiator which adds a fast path and mainly used for stability of LDO (it adds LHP zero)

• Input 1.8V, output 1.6V with load varying from 0 to 50mA, the drop-out voltage achieved is 6mV for no load and 110mV for full load. With load regulation 0.001% and power consumption 200uW(standby). Comparison study of 3 stage nested miller OPAMP and 2 stage Ahuja compensation Jan 2023-May 2023

• Design and implementation of 3 stage nested miller compensation with first stage being telescopic opamp followed by 2 source follower amplifiers.

• Design and implementation of 2 stage Ahuja compensation which include a telescopic opamp and a source follower.

• Results of nested miller DC gain: 107dB, GBW: 6MHz, PM: 520, input referred noise: 60uV/ÖHz, Power:950uW.

• Results of Ahuja compensation DC gain:93dB, PM:600, GBW:12MHz, input referred noise: 67uV/ÖHz, Power: 60uW. Design of a Fully differential OPAMP with common mode feedback Aug 2022-Dec 2022

• Design and layout (common centroid) of Fully differential folded cascode amplifier with DC gain: 61dB, GBW: 130MHz, PM: 720, Slew rate: 100V/us.

• Design of common mode feedback circuit with phase margin of 600. Design of a 3.2GHz Frequency synthesizer for wireless communications with spurs under -70dBc Aug 2022-Dec 2022

• PLL based frequency synthesizer with transistor level design of each block (PFD, Charge Pump, VCO)

• Implemented 31/32 Pre scaler dual modulus frequency divider with sigma delta modulator.

• Designed in IBM 90nm technology and achieved 3.2GHz frequency with phase noise -107dBc/Hz. Hybrid Beamforming in 5G. Aug 2023-Dec 2023

• Using Orthogonal Matching pursuit algorithm both Transmitter and Receiver model is implemented.

• The hybrid beamforming vs digital(precoding) only, hybrid beamforming closely follows precoding spectral efficiency.

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