Earl Davis R&D Electronics' Princpal Engineer Hingham, MA 02043 ad3evx@r.postjobfree.com 781-***-**** Work Experience R&D Electronics' Princpal Engineer REXA Inc June 2012 to Present Responsible for both the hardware and firmware development for the X3 Industrial controller to include all derivatives of the control electronics. Firmware: Lead a team of several firmware engineers to developed real-time embedded processing and GUI/ wireless applications for an Industrial controller. Created infrastructure/processes for creating firmware development using IAR workbench (code development), tortoise SVN (version control), JIRA (bug tracking and work assignments), PC Lint (static analysis) tools and ISO documents for all stages of firmware development. Responsible for the all front panel firmware which used FreeRTOS multitasking RTOS, AES block chaining 128 bit key encryption/decryption over a wireless Bluetooth radio, keyboard, and graphics display. Hardware: Designed and debugged all hardware designs for the X3 system, MCU (ARM9 mixed signal) board, two power boards, power supply, interconnect board, output relay board, switching power supply with UPS back up option, and co-designed the front panel (cortex M3) processor hardware to include wireless Bluetooth communications. LT PSPICE was used for simulations of parts of the hardware design such as second order Butterworth filters, input active low pass filtering coupled with an analog peak detector for monitoring VAC power, low pass filters using LC components (pi filters) to eliminate switching noise from switching power supply, and development of a motion control algorithm for hydraulic actuation. Hardware designs utilize OrCAD 16.6 for schematic capture and responsible for all boards layout utilizing OrCAD 16.6 PCB Editor. Responsible for all aspects of hardware design debugging, test code, documentation, and scheduling for timely deliverables. Designed, debugged hardware and firmware utilizing a TI am3359 for a EtherCat communications board. The AM3359 ARM Cortex A8 processor has two Real-time (PRU) that have been used to communicate with the the modified Ethernet/EtherCat protocols. Early stages of hardware/firmware architectures concepts utilizing Altera Cyclone V Dual Core Cortex ARM9 Soc. Verilog HDL coding is used for the FPGA. OS is under evaluation with Linux, Micruim and FreeRTOS opearting systems. All functional algorithms are being examined by using Matlab/Simulink. http://www.rexa.com/ DSP Embedded Firmware Engineer Volcano Industries, MA January 2011 to June 2012 Real-time DSP embedded software applications for medical heart scanning system. Software is written in C, assembly to run on ADSP-BF527. Developing drivers for UART's, A/D's, and D/A's, SPI (NVRAM and FLASH), as well as I2C devices. Created firmware to download and configure an Vertex 6 Xilinx FPGA http://www.volcanocorp.com/products/ivus-imaging/ Senior Embedded Software Engineer KVH Industries July 2010 to January 2011 Real-time embedded software applications for a tactical navigation systems TACNAVII and TACNAV Light/Heavy configurations. Software was written in C and developed to run on FreeScale Coldfire MC5485 processor. I was involved with all aspects of software drivers as the CAN, TCP/IP, Serial UARTS, A/Ds, and D/As, Temperature Sensors etc.. DOD Secrete Clearance. http://www.thalescomminc.com/content/multiairborneradio.aspx Principle Hardware Engineer Thales Communications, MD August 2008 to July 2010 Technical lead for a "Continuous Phase Frequency Shift" modulator for the Automatic Dependent Surveillance - Broadcast (ADS-B) program. ADS-B is a system by which aircraft and certain equipped surface vehicles can share position, velocity, and other information with one another (and also with ground-based facilities/fixed locations such as air traffic services) via radio broadcast techniques. The raise cosine FIR filter, symbol generator, phase accumulator, and CORDIC are some of the major components within the modulator design. The "Automatic Level Control" ALU incorporating a forward and reverse power feedback closed control loop is part of the output scaling from the CORDIC to the DAC. I was one of the contributing architects for the (Multichannel, Multiband Airborne Radio(MMAR)). As the technical lead, I lead a team of engineers as well as design VOIP hardware. Designed embedded realtime hardware/software ADSP-BF537, VoIP software (G.729ab, G.711) TCP/IP stack, and VHDL/Verilog HDL firmware for a Spartan 3, Spartan 6 Xilinx FPGA, Vertex 4 as well as Actel and Altera FPGA's, experience in language C, C++, assembly within a real-time environment. I have experience with RTOS uClinux, uCos, and Analog Devices VDK real-time kernels as well as Linux device drivers. Active DoD Secret Clearance. http://www.thalescomminc.com/airborne.asp?cart_id= DSP Software Developer Engineer MIT Lincoln Labs October 2003 to June 2008 Embedded real-time DSP (ADSP TS-201) algorithm and software implementation for Transformational Satellite Communications (TSAT), Advanced Extremely High Frequency (AEHF), and (HSV) real-time cryptographic interface between AEHF and base command. Extensive experience in language C within a real-time environment. Active DoD Secret Clearance. Senior Digital Hardware Engineer Herley Industries - Lancaster, PA June 2002 to March 2003 Implemented real-time command, control, and flight algorithms within Actel FPGA's for various cruise, hellfire, and trident missile systems. Main focus was on hardware FPGA's to send back data telemetry information to ground control concerning in flight missile status. MD Lockheed Martin Global Telecommunications April 1984 to June 2002 Senior Member of the Technical Staff DSP Engineer designed low-level Application Programming Interface (API) modules to access and control the board's hardware through the firmware within Altera's FPGA's. These low-level device driver APIs invoke the data controller firmware, as well as interfacing with the DSP modem software. The High-speed QPSK/MFSK/BPSK modem functions were performed between the FPGA core, Analog IF control interface, and ADSP 21060 DSPs. Hardware architecture consisted of two ADSP21060 DSP in a standard multiprocessor environment interfacing to a PowerPC 860. Embedded hardware/firmware for the Video Transpose Buffer Card (VTBC) within the NASA FlexibleRate High Definition Television (HDTV) program. VTBC operated within the transmit and receive filter paths with only a minor firmware change. Receive path received interlaced data field 1, field 2 stored into a memory array. Data was sent to the vertical filter board for further processing. State machines within the Altera PLD/s controlled all major functions. Intel I960 processor was used within the Digital Video MPEG-II multiplexer/demultiplexer to handle user and data traffic control. Made several hardware and firmware adjustments to improve data integrity (i.e. data synchronization, FEC). Modifications were made to the software architecture background and foreground processes to allow high raw-data to be multiplex into the composite multiplexed transport stream. Although, the primary function of this multiplexer is to accept up to 11 MPEG-2 transport streams in RS-422 format and time-multiplex the composite transport stream over HotLink format @270 MBPS and DS3 (with framing). Modified the firmware to synchronize the eleven inputs MPEG-2 transports streams to allow additional FEC coding to be applied on the outgoing composite HotLink data stream. There were a number of state machines used to accommodate this function. Altera's MAX+PLUS II HDL hardware definition language was used to create state machines, logic verification, and timing analysis. Wrote and implemented GUI to operate on Microsoft 95/98/NT. This graphical interface had FoxPro database within the software for customers DVM setups convince. Also, wrote the DVM I960 software to respond to commands from the PC. The software was written in C and inline assemble to maximize time efficiency. Embedded Integrated Receiver Decoder MPEG-II hardware modifications to insure quality and reliability of outgoing video. There were three Altera FPGA 10k series programmable devices connected via the serial passive programming method. FPGA orchestrated the pre-processing and synchronization of the input transport streams. C-Cube embedded MPEG-II decoders were used for decoding the incoming transport stream. DSP Engineer designed and implemented hardware and supporting software for the ITU G.729 Annex A vocoder, Coding of speech at 8Kbit/s using conjugate structure algebraic-code-excited linear-prediction (CS-ACELP). This was used for conducting host voice evaluation lab MOS test. Designed hardware for in-band and out-of-band data synchronization within a multi-processor-pipelined environment. The hardware incorporated two TMS320C31 floating point DSPs. Designed various communication channel impairment models to handle real-time voice processing. The impairments involve are the Rician fading noise models. The hardware was used to corrupt voice PCM data traffic. This accomplished by using TMS320Cxx DSP boards to process data within the voice channel. DSP embedded Engineer designed hardware, firmware, and DSP software for a digital order wire board within the Low Bit Rate Time Division Multiple Access (TDMA), INTELLSAT satellite system. This board utilized two DSP TMS320C31's to process DTMF, standard phone call setup state machines, and methods for testing channel within the TDMA system. I wrote and implemented hard tasking software within a multitasking kernel. DSP embedded Engineer designed non-intrusive backbone analyzer for INMARSAT-M satellite mobile earth stations, STU-III terminal equipment in accordance with COMSAT's secure transmission protocol. Hardware architecture involved two TMS320C30 DSPs, memory, A/Ds, FPGA firmware, and the all the software (i.e. Viterbi Decoder, OEM specific data protocol). DSP embedded Engineer designed hardware, firmware, and software for Facsimile Interface Unit for the INMARSAT-B, INMARSAT M, and aeronautical satellite protocols. Utilized two TMS320C30 TI DSP's, that handled variable rate formatted/deformed satellite facsimile data. Improvements were made to exiting satellite protocol by means of data statistical analysis. Embedded Zilog processor Z8000 was used to interface data I/O and user command. Designed ACTS INTELLSAT's (TDMA) terminal FEC Decoder test sets. The test set has the capability to generate data test patterns corrupted by various values of noise to perform bit error rate (BER) measurements, which normally require several sophisticated pieces of test equipment. The digital noise generator produces samples of Gaussian noise directly I the digital domain. Assisted in developing the FEC Viterbi decoder, which accepts rate 1/2 code data at a bit rates 27.648 Mbit/s over a 16-bit parallel interface, and delivers decoded data at a bit rates of 13.824 Bit/s. DSP Engineer designed hardware, firmware and software for a 4.8Kbit/s encoder of the overall voice encoder/decoder. Hardware architecture included three TMS320C30 DSPs, local and global memory, arbitration logic, phase lock loop circuitry, and A/D and D/As. Awards: Massachusetts Institute of Technology Lincoln Laboratory Team Award in recognition for significant contributions to the Transformational Satellite Communications System. "ACTS" (Advanced Communications Satellite), FEC Viterbi decoder hardware/software implementation. NASA Team Award in recognition for significant contributions to the Advanced Image Processing System Senior Digital Hardware Engineer Ucentric Systems LLC June 2001 to May 2002 Embedded Digital Video Design Engineer implementing a Multi-Media (Video Client) hardware utilizing IBM-STB series processor. Video Client interconnected with a network server to receive MPEG-II data stream over an Ethernet LAN. The Video Client had the ability to decode MPEG II data transport streams and provided several outputs such as s-video, composite video, left/right audio, and digital audio. Designed hardware and firmware for a video remote control utilizing embedded PIC real-time processor. The processor was able to update user code on demand. This function allowed software updates by remote means.