Design Verification Engineer Silicon Validation Expert

Sanchayita Dasmunshi

Email: *************@*****.*** Phone: 551-***-**** LinkedIn: www.linkedin.com/in/sanchayita-dasmunshi Design Verification Engineer with 3.5+ years of silicon validation experience at Micron Technology, specializing in functional correctness, non- deterministic failure detection, and root-cause analysis across test plat forms. Strong foundation in CPU/SoC microarchitecture, control logic, and coverage-driven verification/validation, complemented by graduate-level research in reliability and probabilistic modeling. EDUCATION

Rutgers University-NB, New Jersey 01/2024 -Present (05/2026) MSc. Electrical And Computer Science Engineering (Signals and Information Processing) CGPA: 3.75 CAD VLSI Design System Analysis Machine Vision Intro to Deep Learning Microelectronics Convex Optimization ML Inverse Problem Introduction to Solid States Probabilistic Graphical Models Security Engineering Technical University Munich (TUM) and Nanyang Technological University (NTU), Singapore 08/2019 - 05/2021 MSc. Integrated Circuit Design (ICD)

Digital IC Design (+LAB) Analog IC Design(+LAB) System on Chip Solution Design Methodology and Automation Digital Signal Processing Embedded Systems Design for Testability of VLSI SRM Institute of Science and Technology, India 07/2014 - 05/2018 BTech Electronics and Instrumentation Engineering

WORK EXPERIENCE

Research Assistant :Device Reliability & Transport Modeling 05/2025-Present Rutgers University, Nanofabrication CoRE Facility Rutgers, US

• Analysed charge transport and degradation mechanisms in devices to characterize failure modes and reliability limits.

• Applied physics-based modelling and statistical analysis to distinguish tunnelling vs. defect-assisted conduction paths.

• Correlated fabrication parameters with electrical behaviour to improve device-level correctness and robustness and device reliability. Functional Design Validation- Product Engineer II 05/2021 - 01/2024 Micron Technology Singapore

•Owned post-silicon functional validation of complex memory subsystems across bring-up, stress, and production flows.

• Designed non-deterministic and stress-based validation strategies that uncovered 30% additional corner-case and intermittent failures not detected by deterministic testing.

• Drove root-cause analysis spanning RTL intent, micro-architectural behaviours, waveform-level debug, and silicon anomalies in collaboration with design and architecture teams.

• Built Verilog, Python, and Perl automation for stimulus generation, failure triage and debug analytics, reducing manual effort by 50%.

• Expanded functional coverage using coverage gap analysis and targeted stimulus refinement, achieving 95% system level coverage.

• Defined and tracked validation health metrics (coverage closure, failure density, debug latency) to guide tape-in readiness and risk assessment.

NVE-Product Engineer Intern 07/2020 - 04/2021

Micron Technology Singapore

• Developed automated validation workflows improving repeatability and reducing human error.

• Enhanced deterministic and pseudo-random test flows for early detection of corner-case failures.

• Reduced validation cycle time by 40% through tooling and process optimization. Process Planning & Industrial Engineering 01/2019 - 06/2019 Siemens Limited India

• Automated high-voltage production test flows, improving throughput and hardware test reliability.

• Collaborated with design, production, and test teams to improve process robustness. PROJECTS (UNIVERSITY AND PERSONAL)

Advanced Probabilistic Graphical Model for High-Precision Image Segmentation Rutgers, US 2024

•Designed an undirected Markov Random Field capturing pixel dependencies and implemented loopy belief propagation for approximate MAP inference to separate subtle foreground and background regions.

• Integrated signal-processing preprocessing and tailored likelihood features to improve boundary fidelity.

• Benchmarked against classical thresholding methods, showing stronger robustness to texture variation. Mahala Nobis-Enhanced Non-Local Means Denoising Rutgers, US 2024

• Improved NL-Means similarity metric using Mahala Nobis distance to model correlated patch statistics.

• Reduced speckle noise while preserving critical edges in medical and radar images.

• Implemented a modular Python framework and validated performance with PSNR/RMSE and visual assessment. SKILLS

Hardware Languages & Automation: Verilog, System Verilog,UVM Automation: Python, Perl: Stimulus Generation, Regression Automation, Debug Analytics Silicon & Test: Post-Silicon Validation, ATE (Teradyne Magnum V), High-Speed Interface Testing, Silicon Simulation Correlation AI/ML & Data Methods: Probabilistic Modelling, MRF / Belief Propagation, Statistical Analysis, Anomaly Detection, Data-Driven Triage Workflow: Git, SVN, JIRA.

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